參數(shù)資料
型號(hào)： W9751G6JB-25A
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝： 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84
文件頁(yè)數(shù)： 3/86頁(yè)
文件大?。?/td> 1030K
代理商： W9751G6JB-25A
W9751G6JB
Publication Release Date: Mar. 10, 2010
- 11 -
Revision A02
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
DDR2
-6
67
DDR2
-80
0
DD
R2-1
066
DDR2
-8
00
DDR2-
106
6
D
DR2-
667
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2—Mode Register Set (MRS)
7.2.2
Extend Mode Register Set Commands (EMRS)
7.2.2.1
Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W9751G6JB-3 制造商:Winbond Electronics Corp 功能描述:512MB DDRII
W9751G6KB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
W9751G6KB-18 制造商:Winbond Electronics Corp 功能描述:IC MEMORY
W9751G6KB-25 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6
W9751G6KB25A 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle
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