- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203637 > W946432AD-6 (WINBOND ELECTRONICS CORP) 2M X 32 DDR DRAM, 0.1 ns, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | W946432AD-6 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M X 32 DDR DRAM, 0.1 ns, PQFP100 |
| 文件頁數(shù)： | 37/39頁 |
| 文件大?。?/td> | 577K |
| 代理商： | W946432AD-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁
W946432AD
512K
× 4 BANKS × 32 BITS DDR SDRAM
PRELIMINARY DATA:11/13/01
7
AC CHARACTERISTICS
(0 °C
≤ TA ≤ 70 °C; for –55 / –6 VDD/VDDQ= 2.5V ± 6% for ”-5H” VDD/VDDQ = +2.6V ± 0.1V, VDD = +2.6V ± 0.1V)
PARAMETER
-5H
55
-6
UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX.
DQ output access time from CLK/ CLK
tAC
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
DQS output access time from CLK/ CLK
tDQSCK
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
CLK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock cycle time
tCLK
5
8
5.5
8
6
8
ns
8
DQ and DM input hold time
tDH
1
ns
DQ and DM input setup time
tDS
0.5
ns
Data-out high-impedance time from CLK/ CLK
tHZ
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
Data-out low-impedance time from CLK/ CLK
tLZ
-0.1
0.1
-0.1
0.1
-0.1
0.1
tCK
DQS-DQ Skew (for DQS and associated DQ
signals)
tDQSQ
0.5
ns
DQS-DQ Skew (for DQS and all DQ signals)
tDQSQA
0.45
ns
DQ/DQS output valid time
tDV
0.2
tCK
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS input high pulse width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS input low pulse width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS falling edge to CLK setup time
tDSS
0.2
tCK
DQS falling edge hold time from CLK
tDSH
0.2
tCK
MODE REGISTER SET command cycle time
tMRD
2
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.25
tCK
Address and Control input hold time
tIH
1
ns
Address and Control input setup time
tIS
1
ns
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.4
0.6
0.4
0.6
tCK
ACTIVE to PRECHARGE command
tRAS
35
120K
35
120K
42
120K ns
ACTIVE to ACTIVE/Auto Refresh command
period
tRC
55
60.5
60
ns
Auto Refresh to Active/Auto Refresh command
period
tRFC
65
71
72
ns
ACTIVE to READ or WRITE delay
tRCD
15
16.5
18
ns
PRECHARGE command period
tRP
16
16.5
18
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
10
11
12
ns
Write recovery time
tWR
10
11
12
ns
Auto Precharge write recovery + precharge time
tDAL
25
27.5
30
ns
Internal Write to Read Command Delay
tWTR
2
tCK
9
Exit SELF REFRESH to non-READ command
tXSNR
65
71
72
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
Average Periodic Refresh Interval
tREFI
15.6
us
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W947D6HBHX6E | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| W9602BB | PUSHBUTTON SWITCH, SPST, MOMENTARY, 10A, 28VDC, PANEL MOUNT-THREADED |
| W9605BB | PUSHBUTTON SWITCH, SPST, MOMENTARY, 10A, 28VDC, PANEL MOUNT-THREADED |
| W9606BB | PUSHBUTTON SWITCH, SPDT, MOMENTARY, 10A, 28VDC, PANEL MOUNT-THREADED |
| W9712G8JB-3 | DDR DRAM, PBGA60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9464G6IB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM |
| W9464G6IH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM |
| W9464G6JH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM |
| W9464G6JH-4 | 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
| W9464G6JH-5 | 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復。