參數(shù)資料
型號(hào)： W946432AD-6
廠(chǎng)商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 2M X 32 DDR DRAM, 0.1 ns, PQFP100
文件頁(yè)數(shù)： 10/39頁(yè)
文件大?。?/td> 577K
代理商： W946432AD-6
W946432AD
PRELIMINARY DATE: 11/13/01
18
.
Figure4:tRCD and tRRD Definition
CK
NOP
ACT
Row
Col
Row
Bank x
Bank y
tRRD
tRCD
COMMAND
A0-A10
BA0,BA1
tRCD and tRRD Definition
DON'T CARE
NOP
ACT
NOP
RD/WR
READs
The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is
either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled (A8 = high), the row that
is accessed will start precharge at the completion of the burst. This command cannot be interrupted by any
other command. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is
disabled (A8 = low).
During READ bursts, the valid data-out element from the starting column address will be available following
the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the
next positive or negative clock edge. Figure5: shows general timing. DQS is driven by the DDR SDRAM
along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state
coincident with the last data-out element is known as the read post amble. Upon completion of a burst,
assuming no other commands have been initiated, the DQS will go High-Z.
Data from any READ burst may be concatenated with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data can be maintained. The first data element from the new
burst follows either the last element of a completed burst or the last desired data element of a longer burst
which is being truncated. The new READ command should be issued
x cycles after the first READ
command, where
x equals the number of desired data element pairs (pairs are required by the 32 prefects
architecture). This is shown in Figure6:. A READ command can be initiated on any clock cycle following a
previous READ command. Non-consecutive READ data is shown for illustration in Figure7:. Full-speed
random read accesses within a page (or pages) can be performed as shown in Figure8:.
Data from any READ burst may be truncated with a BURST READ STOP command, as shown in
Figure9:The BURST READ STOP latency is equal to the read ( CAS ) latency.
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be
issued. If truncation is necessary, the BURST READ STOP command must be used, as shown in Figure10:.
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided
that AUTO PRECHARGE was not activated). The PRECHARGE command should be issued
x cycles after
the READ command, where
x equals the number of desired data element pairs. Note that part of the row
precharge time is hIccen during the access of the last data elements.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W9464G6IB 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:1M × 4 BANKS × 16 BITS DDR SDRAM
W9464G6IH 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:1M ?? 4 BANKS ?? 16 BITS DDR SDRAM
W9464G6JH 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:1M ? 4 BANKS ? 16 BITS DDR SDRAM
W9464G6JH-4 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP
W9464G6JH-5 制造商:Winbond Electronics Corp 功能描述:64MBIT DDRI 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 64M 200MHZ 66TSOP
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