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參數資料
| 型號： | W78M32VP110BM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 8M X 32 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數： | 6/51頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | W78M32VP110BM |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M32VP-XBX
January 2010
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
If the system asserts VIH on the WP#/ACC pin, the device
reverts to whether the boot sectors were last set to be
protected or unprotected. That is, sector protection or
unprotection for these sectors depends on whether they
were last protected or unprotected.
The WP#/ACC pin must be held stable during a command
sequence execution. WP# has an internal pull-up; when
unconnected, WP# is set at VIH.
NOTE
If WP#/ACC is at VIL when the device is in the standby mode,
the maximum input load current is increased.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control inputs to prevent unintentional writes
when VCC is greater than VLKO.
WRITE PULSE “GLITCH PROTECTION”
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
POWER-UP WRITE INHIBIT
If WE# = CE# = RESET# = VIL and OE# = VIH during power
up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
POWER CONSERVATION MODES
STANDBY MODE
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at VCC ±
0.3 V. The device requires standard access time (tCE) for
read access, before it is ready to read data. If the device
is deselected during erasure or programming, the device
draws active current until the operation is completed. ICC4
in “DC Characteristics” represents the standby current
specication
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 30 ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. ICC6 represents the automatic sleep mode
current specication.
HARDWARE RESET# INPUT
OPERATION
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP, the device immediately
terminates any operation in progress, tristates all outputs,
and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is
ready to accept another command sequence to ensure
data integrity.
When RESET# is held at VSS ± 0.3 V, the device draws ICC
reset current (ICC5). If RESET# is held at VIL but not within
VSS ± 0.3 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and
thus, a system reset would also reset the Flash memory,
enabling the system to read the boot-up rmware from the
Flash memory.
OUTPUT DISABLE (OE#)
When the OE# input is at VIH, output from the device is
disabled. The outputs are placed in the high impedance
state. (With the exception of RY/BY#.)
SECURED SILICON SECTOR FLASH
MEMORY REGION
Secured Silicon Sector Flash Memory Region The Secured
Silicon Sector provides an extra Flash memory region that
enables permanent part identication through an Electronic
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W78M32VP-110BM | 制造商:White Electronic Designs 功能描述:Flash Module Parallel 256Mbit |
| W78M32V-XBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M64VP110SBM | 制造商:Microsemi Corporation 功能描述:8MX64 FLASH 3.3V PAGE MODE - Bulk |
| W78M64V-XSBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash MCP |
| W78NCSX-23 | 功能描述:低信號繼電器 - PCB 4PDT 3A 24VDC IND RoHS:否 制造商:NEC 觸點形式:2 Form C (DPDT-BM) 觸點電流額定值: 線圈電壓:5 V 最大開關電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
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