- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203627 > W3H32M72E-400SB2M (WHITE ELECTRONIC DESIGNS CORP) 32M X 72 DDR DRAM, 0.6 ns, PBGA208 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3H32M72E-400SB2M |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| 封裝： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁(yè)數(shù)： | 8/30頁(yè) |
| 文件大?。?/td> | 0K |
| 代理商： | W3H32M72E-400SB2M |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)
W3H32M72E-XSB2X
16
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2009
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes appear on page 9
Function
CKE
CS#
RAS#
CAS#
WE#
BA1
BA0
A12
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
LLLL
BA
OP Code
2
REFRESH
H
L
H
XXXX
SELF-REFRESH Entry
H
L
H
XXXX
SELF-REFRESH Exit
LH
H
XXX
XXXX
7
L
HHH
Single bank precharge
HH
L
H
L
X
L
X
2
All banks PRECHARGE
HH
L
H
L
X
H
X
Bank activate
H
L
H
L
BA
Row Address
WRITE
HH
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
HH
L
H
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
LH
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
LH
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
XXXX
Device DESELECT
H
X
H
XXXXXXX
POWER-DOWN entry
HL
H
XXX
XXXX
4
L
HHH
POWER-DOWN exit
LH
H
XXX
XXXX
4
L
HHH
Note: 1. All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA12 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a dened logic level).
7. Self refresh exit is asynchronous.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3HG2128M72AER403AD6SG | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| W3HG2128M72AER534AD6MG | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| W3HG2128M72AER665AD6SG | 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| W3HG2128M72AER534AD6SG | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| W51-C112B1-20 | ROCKER SWITCH, SPDT, LATCHED, 20A, 50VDC, THROUGH HOLE-RIGHT ANGLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H32M72E-400SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H32M72E-400SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H32M72E-400SBM | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk |
| W3H32M72E-533ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-533ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。