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參數(shù)資料
| 型號(hào)： | W155 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum Frequency Timing Generator(寬頻譜頻率定時(shí)發(fā)生器) |
| 中文描述： | 擴(kuò)頻頻率定時(shí)發(fā)生器（寬頻譜頻率定時(shí)發(fā)生器） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 85K |
| 代理商： | W155 |
Spread Spectrum Frequency Timing Generator
W155
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
September 29, 1999, rev. **
408-943-2600
Features
Generates a spread spectrum timing signal (SYSCLK)
and a non-spread signal (USBCLK)
Requires a 14.318-MHz crystal for operation
Supports MIPS microprocessor clock frequencies
Reduces peak EMI by as much as 12 dB
Integrated loop filter components
Cycle-to-cycle jitter = 250 ps (max)
Operates with a 3.3 or 5.0V power supply
Spread output is selectable from 10 to 133 MHz
TEST mode supports modulation off (High-Z) and spe-
cial test input reference frequency
Guaranteed 45/55 duty cycle
Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline
Integrated Circuit)
Overview
The W155 incorporates the latest advances in PLL-based
spread spectrum frequency synthesizer technology. By fre-
quency modulating the SYSCLK output with a low-frequency
carrier, peak EMI can be greatly reduced in a system. Use of
this technique allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system that uses the W155, not only is EMI reduced in the
various clock lines, but also in all signals which are synchro-
nized to SYSCLK. Therefore, the benefits of using this tech-
nique increase with the number of address and data lines in
the system.
The W155 is specifically targeted toward MIPS microproces-
sor based systems where EMI is of particular concern. Each
device uses a single 14.318-MHz crystal to generate a select-
able spread spectrum output and an unmodulated 48-MHz
USB Output.
The spreading function can be disabled by taking the SSON#
pin high. Spread percentage can be selected with the SS%
input (see
Table 2
below).
Table 1. Frequency Selection (14.318-MHz Reference)
FS3
FS2
FS1
FS0
SYSCLK
(Output Freq.)
0
0
0
0
133.3 MHz
0
0
0
1
120 MHz
0
0
1
0
100 MHz
0
0
1
1
74.77 MHz
0
1
0
0
70 MHz
0
1
0
1
66.6 MHz
0
1
1
0
60 MHz
0
1
1
1
50 MHz
1
0
0
0
40 MHz
1
0
0
1
33.33 MHz
1
0
1
0
30 MHz
1
0
1
1
25 MHz
1
1
0
0
20 MHz
1
1
0
1
16.67 MHz
1
1
1
0
12 MHz
1
1
1
1
10 MHz
Table 2. Spread Percentage Selection
SS%
Spread Percentage
0
–1.25%
1
–3.75%
Pin Configuration
TEST
VDD
USBCLK/SS%*
GND
SYSCLK
GND
FS0*
SSON#^
16
15
14
13
12
11
10
9
VDD
X1
X2
GND
FS3*
VDD
FS2*
FS1*
1
2
3
4
5
6
7
8
W
[1]
Note:
1.
Internal pull-up resistor present on inputs marked with ‘*’ and pull-down
resistor present on input marked with ‘^’.
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