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參數(shù)資料
| 型號： | W156C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum FTG for VIA MVP4(應(yīng)用于VIA MVP4的寬頻譜FTG) |
| 中文描述： | 擴(kuò)頻FTG威盛MVP4（應(yīng)用于威盛MVP4的寬頻譜FTG） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 157K |
| 代理商： | W156C |
PRELIMINARY
Spread Spectrum FTG for VIA MVP4
W156C
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
November 17, 1999, rev. **
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Single-chip implementation
Four copies of CPU output
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz output for SIO
Two buffered reference outputs
Thirteen SDRAM outputs provide support for 3 DIMMs
Supports frequencies up to 124 MHz
I
2
C interface for programming
Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter:.......................................... 250 ps
CPU to CPU Output Skew: ......................................... 300 ps
CPU to PCI Output Skew:.................................. 1.5 to 4.0 ns
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
= V
DDQ_CPU
=.............................................. 3.3V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................4.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew...............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3
FS2
FS1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
CPU, SDRAM
(MHz)
60
66.8
70
75
97
83.3
95.25
100
75
96.2
83.3
105
110
115
120
124
PCI_F, 1:5
(MHz)
30 (CPU/2)
33.4 (CPU/2)
35 (CPU/2)
25 (CPU/3)
32.3 (CPU/3)
27.7 (CPU/3)
31.75 (CPU/3)
33.3 (CPU/3)
37.5 (CPU/2)
32.0 (CPU/3)
41.7 (CPU/2)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
41.3 (CPU/3)
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I
2
C is a trademark of Philips Corporation.
Logic Block Diagram
Pin Configuration
[1, 2]
REF1/FS2
CPU1:3
OSC
PLL Ref Freq
PLL 1
X2
X1
Stop
Clock
Stop
Clock
PCI2
PCI3
PCI4
48MHz/FS0
VDDQ3
PLL2
÷2,3
CLK_STOP#
PCI5
VDDQ3
Logic
SCLK
Control
SDRAM0:11
SDRAMIN
12
Stop
Clock
CPU_F
÷2
SDRAM_F
REF0/(PCI_STOP#)
PCI_F/MODE
PCI1/FS3
XTAL
Stop
Stop
VDDQ3
I
2
C
SDATA
I/O Pin
Stop
VDDQ3
REF0/(PCI_STOP#)*
GND
X1
X2
VDDQ3
PCI_F/MODE*
PCI1/FS3*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
I
2
C
{
GND
SDATA
SCLK
W
REF1/FS2*
VDDQ_CPU
CPU_F
CPU1
GND
CPU2
CPU3
CLK_STOP#*
GND
SDRAM_F
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Notes:
1.
Internal pull-up resistors of 250 k
to 3.3V present on inputs indicated
with *.
Internal pull-up resistors should not be relied upon for setting I/O pins
HIGH. Pin function with parentheses determined by MODE pin resistor
strapping.
2.
VDDQ3
VDDQ_CPU
VDDQ3
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