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參數(shù)資料
| 型號： | W161 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 133-MHz Spread Spectrum FTG for Pentium II Platforms |
| 中文描述： | 133 - MHz的擴頻FTG的奔騰II平臺 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 129K |
| 代理商： | W161 |
PRELIMINARY
133-MHz Spread Spectrum FTG for Pentium II Platforms
W161
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 13, 1999, rev. **
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
Three copies of CPU outputs at 100 or 133 MHz
Three copies of 66-MHz output at 3.3V
Ten copies of PCI clocks at 33 MHz, 3.3V
Two copies of 14.318-MHz reference output at 3.3V
One copy of 48-MHz USB clock
One copy of CPU-divide-by-2 output as reference input
to Direct Rambus Clock Generator (Cypress W134)
Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... V
DDQ2
= 2.5V±5%
V
DDQ3
= 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew:...................................... 175 ps
IOAPIC, 3V66 Output Skew:....................................... 250 ps
PCI0:9 Output Skew: .................................................. 500 ps
Duty Cycle: ...................................................................45/55
Spread Spectrum Modulation:..................................... –0.5%
CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Table 1. Pin Selectable Frequency
SEL133/100#
SEL1
0
0
0
SEL0
0
1
0
Function
0
0
1
All outputs Three-State
(Reserved)
Active 100-MHz, 48-MHz
PLL inactive
Active 100-MHz, 48-MHz
PLL active
Test Mode
(Reserved)
Active 133-MHz, 48-MHz
PLL inactive
Active 133-MHz, 48-MHz
PLL active
0
1
1
1
1
1
0
0
1
0
1
0
1
1
1
Block Diagram
Pin Configuration
REF_[0:1]
CPU_[0:2]
CPUdiv2
3V66_[0:2]
XTAL
OSC
PLL 1
SPREAD#
SEL0
SEL1
SEL133/100#
X2
X1
PCI_[0:9]
IOAPIC
48MHz
PLL2
÷2
Power
Down
Logic
Three-state
Logic
÷2/÷1.5
÷2
÷2
2
3
3
9
PWRDWN#
REF0
REF1
VDDQ3
X1
X2
GND
PCI0
PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
W
GND
VDDQ2
IOAPIC
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PWRDWN#*
SPREAD#*
SEL1*
SEL0*
VDDQ3
48MHz
GND
SEL133/100#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note:
1.
Internal 250-k
pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
[1]
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