參數(shù)資料
型號(hào)： W150
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： 440BX AGPset Spread Spectrum Frequency Synthesizer(440BX AGP裝置寬頻譜頻率合成器)
中文描述： 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, SSOP-56
文件頁(yè)數(shù)： 1/14頁(yè)
文件大小： 155K
代理商： W150
PRELIMINARY
440BX AGPset Spread Spectrum Frequency Synthesizer
W150
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 10, 2000, rev. *A
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
Single chip system frequency synthesizer for Intel
440BX AGPset
Three copies of CPU output
Seven copies of PCI output
One 48-MHz output for USB / One 24-MHz for SIO
Two buffered reference outputs
Two IOAPIC outputs
17 SDRAM outputs provide support for 4 DIMMs
Supports frequencies up to 150 MHz
I
2
C interface for programming
Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
V
DDQ3
: .................................................................... 3.3V±5%
V
DDQ2
: .................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Skew:..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3
FS2
FS1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
CPU_F, 1:2
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 0:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Intel is a registered trademark of Intel Corporation. I
2
C is a trademark of Philips Corporation.
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Logic Block Diagram
Pin Configuration
[1]
VDDQ3
REF0/(PCI_STOP#)
VDDQ2
IOAPIC_F
CPU1
CPU2
PCI_F/MODE
OSC
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2
VDDQ3
Stop
Stop
PCI1
PCI2
PCI3
PCI5
VDDQ3
48MHz/FS1
VDDQ3
PLL2
÷2,3,4
CPU_F
CLK_STOP#
IOAPIC0
PCI4
I
2
C
Logic
SCLK
I/O Pin
SDRAM0:15
SDRAM_F
SDRAMIN
16
PCI0/FS3
CStop
CStop
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRGND
W
VDDQ2
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ2
CPU2
GND
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
24MHz/FS0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDATA
SCLK
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