參數(shù)資料
型號(hào): VV5410
廠商: 意法半導(dǎo)體
英文描述: Mono and Colour Digital Video CMOS Image Sensors
中文描述: 莫諾和數(shù)字視頻彩色CMOS圖像傳感器
文件頁數(shù): 52/105頁
文件大?。?/td> 489K
代理商: VV5410
VV5410 & VV6410
Digital Video Interface Format
cd5410-6410f-3-0.fm
Commercial in confidence
52/105
8.8.2
Under the control of the serial interface the sensor analog circuitry can be powered down and then repowered. When the low-
power bit is set via the serial interface, all the data bus lines will go high at the end of the end of frame line of the current frame.
At this point the analog circuits in the sensor will power down. The system clock must remain active for the duration of low power
mode.
Low-Power Mode (Figure 30)
During low power mode only the analog circuits are powered down, the values of the serial interface registers e.g. exposure and
gain are preserved. The internal frame timing is reset to the start of a video frame on exiting low-power mode. In a similar manner
to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9
H
and 6 - or
equivalent for the alternative ouput databus widths - to allow the host to re-confirm its sampling position. Then three frames later
the first start of frame line is generated.
8.8.3
Sleep mode is similar to the low-power mode, except that analog circuitry remains powered. When the sleep command is
received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current
frame. Again the system clock must remain active for the duration of sleep mode.
Sleep Mode
When sleep mode is disabled, the CMOS sensor’s frame timing is reset to the start of a frame. During the first frame after exiting
from sleep mode the data bus will remain high, while the exposure value propagates through the pixel array. At the start of the
second frame the first start of field line will be generated.
8.8.4
To allow the sensor to enter and exit the low power and sleep modes the system clock, CLKI, must be active.
System clock status during sensor low-power modes
8.9
Under the control of the SUSPEND pin VV5410/VV6410 can be forced into an ultra low power mode. The sensor will consume
less than 80uA of current while suspended. While the sensor is in this mode video output is turned off and no serial
communications can occur.
Suspend mode
The SUSPEND mode is effectively identical to a power on reset - all the video timing blocks within the sensor are reset as are the
contents of the serial interface, therefore the user will have to perform a compete reconfiguration of the device on exitting
SUSPEND. The sensor will also repeat the full 4 field power up sequence.
8.10 Data Qualification Clock, QCK
VV5410/VV6410 provides a data qualification clock, (see Figure 31), to qualify the information output on data bus. The sensor
can generate two styles of qualification clock:
Fast QCK, clocks at nibble rate. The falling edge of this clock qualifies data
Mode
10-bit Value
Output Data Bus Pattern
4-Wire
258
H
9
H
/6
H
(1001
2
/0110
2
)
5-Wire
136
H
09
H
/16
H
(01001
2
/10110
2
)
8-Wire
096
H
/ 069H
25
H
/1A
H
(00100101
2
/00011010
2
Table 16 : Output Data Bus Patterns for determination of Best Sampling Position
Mode
Description
Approx. Sensor Current
Suspend
Sensor in lowest power state. Suspend has been
asserted by host.
c.80uA
Table 17 : VV5410/VV6410 suspend mode power consumption
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