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參數(shù)資料
| 型號： | VV5404 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CIF FORMAT DIGITAL IMAGE SENSOR |
| 中文描述： | CIF格式的數(shù)字圖像傳感器 |
| 文件頁數(shù)： | 43/54頁 |
| 文件大小： | 786K |
| 代理商： | VV5404 |
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VV5404 & VV6404
CD5404-6404F-A
43/54
6.8
Synchronising 2 or More Cameras
A rising edge on the SIN pin re-synchronises the sensor’s internal video timing logic and clock generators to 5 pixels
before the end of the start of frame control sequence in line 0 (assuming the Setup2 register has been programmed
correctly with the value 30). By supplying an external timing signal to SIN, with a period equal to 2 frames (see Figure
28), 2 or more cameras can be synchronised together.
For proper synchronisation, the pixel counter register Setup2 must be written with 30, which will cause SIN to reset
the video timing to 5 pixel periods before the end of the start of frame control sequence. SIN is sampled internally by
the system clock, CKI. If all cameras are supplied with the same clock signal then the reset generated by SIN will
synchronise all the cameras to the same point in time. However, if the cameras being synchronised are running at
the same frequency but each camera has its own crystal, then there could be upto one system clock period of skew
between the cameras. This skew will vary over time due to the slight mis-matches between frequencies of the different
crystals.
.
CLKI
(MHz)
Clock Div Reg
Divisor
Pixel
Frequency
(MHz)
Frame rate (fps)
Comments
bit 1
bit 0
30 fps
25 fps
7.15909
0
0
2
3.57954
30.0
25.0
Default
7.15909
0
1
4
1.78977
15.0
12.5
7.15909
1
0
8
0.89489
7.50
6.25
7.15909
1
1
16
0.44744
3.75
3.125
Table 29 : Clock Divisors for an externally generated clock signal.
CLKI
(MHz)
Clock Div Reg
Divisor
Pixel
Frequency
(MHz)
Frame rate (fps)
Comments
bit 1
bit 0
30 fps
25 fps
14.31818
0
0
2
7.15909
Not Valid
14.31818
0
1
4
3.57954
30.0
25.0
14.31818
1
0
8
1.78977
15.0
12.5
14.31818
1
1
16
0.89489
7.50
6.25
Table 30 : Clock Divisors for a 14.31818 MHz Crystal
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