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參數(shù)資料
| 型號(hào)： | VV5404 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CIF FORMAT DIGITAL IMAGE SENSOR |
| 中文描述： | CIF格式的數(shù)字圖像傳感器 |
| 文件頁(yè)數(shù)： | 30/54頁(yè) |
| 文件大?。?/td> | 786K |
| 代理商： | VV5404 |
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VV5404 & VV6404
CD5404-6404F-A
30/54
A detailed description of each register follows. The address indexes are shown as binary numbers in brackets [].
Index
Name
Length
R/W
Default
Comments
S
000_0000
000_0001
000_0010
000_0011
000_0100
000_0101
000_011x
000_1xxx
001_0000
001_0001
001_0010
deviceH
deviceL
status0
line_countH
line_countL
Unused
Unused
Unused
setup0
setup1
setup2
8
8
8
8
8
RO
RO
RO
RO
RO
0001 1001
2
0100 0000
2
0000 1000
2
Chip identification number
including revision indicator
Current line counter MSB value
Current line counter LSB value
S
8
8
8
R/W
R/W
R/W
0001 0001
2
1100 0001
2
31
Contains pixel counter reset
value used by external sync.
001_0011
001_0100
001_0101
001_011x
001_1xxx
010_0000
010_0001
010_0010
010_0011
010_0100
010_0101
010_0110
010_0111
010_1xxx
111_0000
111_0001
111_0010
111_0011
111_0100
111_0101
111_0110
111_0111
111_1000
111_1001
111_101x
111_11xx
Reserved
setup4
setup5
Unused
Unused
fineH
fineL
coarseH
coarseL
gain
clk_div
Unused
Unused
Unused
Reserved
Reserved
Reserved
Unused
Reserved
Reserved
cr
as0
Reserved
Unused
Unused
Unused
8
8
R/W
R/W
0
0
FST and QCK mode selects
FST and QCK mapping mode.
E
8
8
8
8
3
2
R/W
R/W
R/W
R/W
R/W
R/W
0
Fine exposure.
302
Coarse exposure
0
0
ADC Pre-amp gain Setting
Clock division
S
8
8
R/W
R/W
0000 0000
2
0100 0100
2
Control Register
ADC Setup Register
Table 8 : Serial Interface Address Map.
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