參數(shù)資料
型號: VRS550-QLI25
廠商: Electronic Theatre Controls, Inc.
英文描述: VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述: VRS550 - 8KB閃存,256B的RAM,25MHz的,8位微控制器VRS560 - 16kB的閃存,256B的RAM,25MHz的,8位微控制器
文件頁數(shù): 8/40頁
文件大?。?/td> 868K
代理商: VRS550-QLI25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
8
Description of Peripherals
System Control Register
The register represented in the following table is used
for system control. The WDRESET bit (7) indicates if
the system has been reset due to the overflow of the
Watch Dog Timer.
The bit 0 of the SYSCON register is the ALE output
inhibit bit. Setting this bit to 1 will inhibit the Fosc/6
clock signal output to the ALE pin.
T
ABLE
7:
S
YSTEM
C
ONTROL
R
EGISTER
(SYSCON) – SFR BF
H
7
6
5
WDRESET
Bit
Mnemonic
7
4
Unused
3
2
1
0
XRAME
ALEI
Description
This is the Watch Dog Timer reset bit. It
will be set to 1 when the reset signal
generated by WDT overflows.
-
-
-
-
-
-
ALE output inhibit bit, which is used to
reduce EMI.
WDRESET
6
5
4
3
2
1
0
Unused
Unused
Unused
Unused
Unused
Unused
ALEI
Power Control Register
The VRS550 / VRS560 devices provide two power
saving modes: Idle and Power Down. These two
modes serve to reduce the power consumption of the
device.
In Idle mode, the processor is stopped but the oscillator
is still running. The content of the RAM, I/O state and
SFR registers are maintained. Timer operation is
maintained, as well as the external interrupts.
This mode is useful for applications in which stopping
the processor to save power is required. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator of the VRS550 /
VRS560 is stopped. This means that all the peripherals
are disabled. The content of the RAM and the SFR
registers, however, is maintained.
The minimum VCC in Power down Mode is 2V
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
T
ABLE
8:
P
OWER
C
ONTROL
R
EGISTER
(PCON) - SFR 87
H
7
6
5
Unused
Bit
Mnemonic
7
SMOD
4
3
2
1
0
RAM1
RAM0
Description
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
General Purpose Flag
General Purpose Flag
Power down mode control bit
Idle mode control bit
6
5
4
3
2
1
0
GF1
GF0
PDOWN
IDLE
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VRS560-PAC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PLC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PLI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU