
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
16
Timer 2
Timer 2 of the VRS550 / VRS560 devices is a 16-bit
Timer/Counter. Similar to Timers 0 and 1, Timer 2 can
operate either as an event counter or as a timer. The
user may switch functions by writing to the C/T2 bit
located in the T2CON special function register. Timer 2
has three operating modes: “Auto-Load” “Capture”, and
“Baud Rate Generator”. The T2CON SFR configures
the modes of operation of Timer 2. The next table
describes each bit in the T2CON special function
register.
T
ABLE
14:
T
IMER
2 C
ONTROL
R
EGISTER
(T2CON) –SFR C8
H
7
6
5
TF2
EXF2
RCLK
Bit
Mnemonic
Description
7
TF2
Timer 2 Overflow Flag: Set by an overflow
of Timer 2 and must be cleared by
software. TF2 will not be set when either
RCLK =1 or TCLK =1.
6
EXF2
Timer 2 external flag change in state occurs
when either a capture or reload is caused
by a negative transition on T2EX and
EXEN2=1. When Timer 2 is enabled,
EXF=1 will cause the CPU to Vector to the
Timer 2 interrupt routine. Note that EXF2
must be cleared by software.
5
RCLK
Serial Port Receive Clock Source.
1: Causes Serial Port to use Timer 2
overflow pulses for its receive clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the Serial Port receive clock.
4
TCLK
Serial Port Transmit Clock.
1: Causes Serial Port to use Timer 2
overflow pulses for its transmit clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the Serial Port transmit clock.
3
EXEN2
Timer 2 External Mode Enable.
1: Allows a capture or reload to occur as a
result of a negative transition on T2EX if
Timer 2 is not being used to clock the Serial
Port.
0: Causes Timer 2 to ignore events at
T2EX.
2
TR2
Start/Stop Control for Timer 2.
1: Start Timer 2
0: Stop Timer 2
1
C/T2
1: External event counter falling edge
triggered.
0: Internal Timer (OSC/12)
4
3
2
1
0
TCLK
EXEN2
TR2
C/T2
CP/RL2
Timer or Counter Select (Timer 2)
0
CP/RL2
Capture/Reload Select.
1: Capture of Timer 2 value into RCAP2H,
RCAP2L is performed if EXEN2=1 and a
negative transitions occurs on the T2EX
pin. The capture mode requires RCLK and
TCLK to be 0.
0: Auto-reload reloads will occur either with
Timer 2 overflows or negative transitions at
T2EX when EXEN2=1. When either RCK
=1 or TCLK =1, this bit is ignored and the
timer is forced to auto-reload on Timer 2
overflow.
As shown below, there are different possible
combinations of control bits that may be used for the
mode selection of Timer 2.
T
ABLE
15:
T
IMER
2 M
ODE
S
ELECTION
B
ITS
RCLK + TCLK
CP/RL2 TR2 MODE
0
0
1
16-bit Auto-
Reload Mode
16-bit Capture
Mode
Baud Rate
Generator Mode
Off
0
1
1
1
X
1
X
X
0
The details of each mode are described below.
Capture Mode
In Capture Mode the EXEN2 bit value defines if the
external transition on the T2EX pin will be able to
trigger the capture of the timer value.
When EXEN2 = 0, Timer 2 acts as a 16-bit timer or
counter, which, upon overflowing, will set bit TF2
(Timer 2 overflow bit). This overflow can be used to
generate an interrupt.
F
IGURE
14:
T
IMER
2
IN
C
APTURE
M
ODE
F
OSC
÷12
TIMER
COUNTER
C/T2
0
1
T2 Pin
TR2
T2 EX Pin
0
7
0
7
0
7
0
7
Timer 2
EXF2
EXEN2
RCAP2L
RCAP2H
TL2
TH2
TF2