參數(shù)資料
型號(hào)： VRS550-QLI25
廠商： Electronic Theatre Controls, Inc.
英文描述： VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述： VRS550 - 8KB閃存，256B的RAM，25MHz的，8位微控制器VRS560 - 16kB的閃存，256B的RAM，25MHz的，8位微控制器
文件頁數(shù)： 25/40頁
文件大小： 868K
代理商： VRS550-QLI25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
25
Interrupts
The VRS550 and VRS560 have 8 interrupt sources (9
if we include the WDT) and 7 interrupt vectors
(including reset) to handle them.
The interrupt can be enabled via the IE register shown
below:
T
ABLE
18:
IEN0 I
NTERRUPT
E
NABLE
R
EGISTER
–SFR A8
H
7
6
5
EA
-
ET2
Bit
Mnemonic
7
EA
4
ES
3
2
1
0
ET1
EX1
ET0
EX0
Description
Disables All Interrupts
0: no interrupt acknowledgment
1: Each interrupt source is individually
enabled or disabled by setting or clearing
its enable bit.
Reserved
Timer 2 Interrupt Enable Bit
Serial Port Interrupt Enable Bit
Timer 1 Interrupt Enable Bit
External Interrupt 1 Enable Bit
Timer 0 Interrupt Enable Bit
External Interrupt 0 Enable Bit
6
5
4
3
2
1
0
-
ET2
ES
ET1
EX1
ET0
EX0
The following figure illustrates the various interrupt
sources on the VRS550 / VRS560.
F
IGURE
21:
I
NTERRUPT
S
OURCES
IE0
IT0
INT0
TF0
IE1
IT1
INT1
TF1
T1
RI
TF2
EXF2
INTERRUPT
SOURCES
Interrupt Vectors
The table below specifies each interrupt source, its flag
and its vector address.
T
ABLE
19:
I
NTERRUPT
V
ECTOR
C
ORRESPONDING
F
LAGS ANS
V
ECTOR
A
DDRESS
Interrupt Source
Flag
Vector
Address
RESET (+ WDT)
INT0
Timer 0
INT1
Timer 1
Serial Port
Timer 2
WDRESET
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
0000h
0003h
000Bh
0013h
001Bh
0023h
002Bh
External Interrupts
The VRS550 and the VRS560 have two external
interrupt inputs named INT0 and INT1. These interrupt
lines are shared with P3.2 and P3.3.
The bits IT0 and IT1 of the TCON register determine
whether the external interrupts are level or edge
sensitive.
If ITx = 1, the interrupt will be raised when a 1-> 0
transition occurs at the interrupt pin. For the interrupt
to be noticed by the processor, the duration of the sum
high and low condition must be at least equal to 12
oscillator cycles.
If ITx = 0, the interrupt will occur when a logic low
condition is present on the interrupt pin.
The state of the external interrupt, when enabled, can
be monitored using the flags, IE0 and IE1 of the TCON
register that are set when the interrupt condition
occurs.
In the case where the interrupt was configured as edge
sensitive, the associated flag is automatically cleared
when the interrupt is serviced.
If the interrupt is configured as level sensitive, then the
interrupt flag must be cleared by the software.
相關(guān)PDF資料
PDF描述
VRS550-QLC25 VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS550-QAI25 VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VRS560 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PLC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PLI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
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