參數(shù)資料
型號: VRS550-PAI25
廠商: Electronic Theatre Controls, Inc.
英文描述: VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述: VRS550 - 8KB閃存,256B的RAM,25MHz的,8位微控制器VRS560 - 16kB的閃存,256B的RAM,25MHz的,8位微控制器
文件頁數(shù): 27/40頁
文件大小: 868K
代理商: VRS550-PAI25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
27
Modifying the Interrupt Order of Priority
The VRS550 / VRS560 allows the user to modify the
natural priority of the interrupts. One may modify the
order by programming the bits in the IP (Interrupt
Priority) register. When any bit in this register is set to
1, it gives the corresponding source a greater priority
than interrupts coming from sources that don’t have
their corresponding IP bit set to 1.
The IP register is represented in the table below.
T
ABLE
21:
IP I
NTERRUPT
P
RIORITY
R
EGISTER
–SFR B8
H
7
6
5
EA
-
ET2
Bit
Mnemonic
7
-
6
-
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Watch Dog Timer
4
ES
3
2
1
0
ET1
EX1
ET0
EX0
Description
Gives Timer 2 Interrupt Higher Priority
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
The Watch Dog Timer (WDT) is a 16-bit free-running
counter that generates a reset signal if the counter
overflows. The WDT is useful for systems that are
susceptible to noise, power glitches and other
conditions that can cause the software to go into
infinite dead loops or runaways. The WDT function
gives the user software a recovery mechanism from
abnormal software conditions.
The Watch Dog Timer of the VRS550 and VRS560
devices is driven by the oscillator.
To enable the WDT, the user must set bit 7 (WDTE) of
the WDTCON register to 1. Once WDTE has been set
to 1, the 16-bit counter will start to count with the
selected time base source clock configured in
WDPS2~WDPS0. The Watch Dog Timer will generate
a reset signal if an overflow has taken place.
The WDTE bit will be cleared to 0 automatically when
the device is reset by either the hardware or a WDT
reset.
Once the WDT is enabled, the user software must
clear it periodically. In the case where the WDT is not
cleared, its overflow will trigger a reset of the device.
The user should check the WDRESET bit of the
SYSCON register whenever an unpredicted reset has
taken place.
The WDT timeout delay can be adjusted by configuring
the clock divider input for the time base source clock of
the WDT. To select the divider value, bit2-bit0
(WDPS2~WDPS0) of the Watch Dog Timer Control
Register (WDTCON) should be set accordingly.
Clearing the WDT is accomplished by setting the CLR
bit of the WDTCON to 1. This action will clear the
contents of the 16-bit counter and force it to restart.
Watch Dog Timer Registers
Three registers of the VRS550/VRS560 devices are
associated with the Watch Dog Timer: WDTCON, the
WDTLOCK and the SYSCON registers. The WDTCON
register allows the user to enable the WDT, to clear the
counter and to divide the clock source. The WDRESET
bit of the SYSCON register indicates whether the
Watch Dog Timer has caused the device reset.
T
ABLE
22:
W
ATCHDOG
T
IMER
R
EGISTERS
: WDTCON – SFR 9F
H
7
6
WDTE
Unused
Bit
Mnemonic
7
WDTE
6
Unused
5
WDCLR
[4:3]
Unused
2
1
0
5
4
Unused
3
2
1
0
WDCLR
WDTPS [2:0]
Description
Watch Dog Timer Enable Bit
-
Watch Dog Timer Counter Clear Bit
-
WDPS [2:0]
Watchdog Timer Clock Source Divider
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