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參數資料
| 型號： | VRS550-PAI25 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
| 中文描述： | VRS550 - 8KB閃存，256B的RAM，25MHz的，8位微控制器VRS560 - 16kB的閃存，256B的RAM，25MHz的，8位微控制器 |
| 文件頁數： | 22/40頁 |
| 文件大?。?/td> | 868K |
| 代理商： | VRS550-PAI25 |
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
22
Mode 2 and 3: Additional Information
As mentioned earlier, for an operation in these modes,
11 bits are transmitted through TXD or received
through RXD. The signal comprises: a logical low Start
bit, 8 data bits (LSB first), a programmable 9
th
data bit,
and one logical high Stop bit.
On transmit, (TB8 in SCON) can be assigned the value
of 0 or 1. On receive; the 9
th
data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/32
or 1/64 the oscillator frequency in Mode 2. Mode 3
may have a variable baud rate generated from either
Timer 1 or Timer 2 depending on the states of TCLK
and RCLK.
Transmission in Mode 2 and Mode 3
The transmission is initiated by any instruction that
makes use of SBUF as the destination register. The 9
th
bit position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also informs the TX
control unit that a transmission has been requested.
After the next rollover in the divide-by-16 counter, a
transmission actually begins at T1 of the machine
cycle. The bit times are synchronized to the divide-by-
16 counter and not to the “write to SBUF” signal, as in
the previous mode.
Transmissions begin when the SEND signal is
activated, which places the Start bit at TXD. Data is
activated one bit time later. This activation enables the
output bit of the transmit shift register to TXD. The first
shift pulse occurs one bit time after that.
The first shift clocks a Stop bit (1) into the 9
th
bit
position of the shift register to TXD. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, the stop bit is
just to the left of TB8, and all positions to the left of that
contain zeros. This condition signals to the TX control
unit to shift one more time and set TI, while
deactivating SEND. This occurs at the 11
th
divide-by-16
rollover after “write to SBUF”.
Reception in Mode 2 and Mode 3
One to zero transitions at RXD initiate reception. It is
for this reason that RXD is sampled at a rate of 16
multiplied by the baud rate that has been established.
When a transition is detected, the 1FFh is written into
the input shift register and the divide-by-16 counter is
immediately reset.
During the 7
th
, 8
th
and 9
th
counter states of each bit
time; the bit detector samples the value of RXD. The
accepted value is the value that was seen in at least
two of the three samples. If the value accepted during
the first bit time is not zero, the receive circuits are
reset and the unit goes back to searching for another
one to zero transition. If the start bit is valid, it is shifted
into the input shift register, and the reception of the rest
of the frame will proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register (9-bit
register), it tells the RX control block to do one more
shift, to set RI, and to load SBUF and RB8. The signal
to set RI and to load SBUF and RB8 will be generated
if, and only if, the following conditions are satisfied at
the instance when the final shift pulse is generated:
- Either SM2 = 0 or the received 9
th
bit is equal to 1
- RI = 0
If both conditions are met, the 9
th
data bit received
goes into RB8, and the first 8 data bits go into SBUF. If
one of these conditions is not met, the received frame
is completely lost. One bit time later, whether the
above conditions are met or not, the unit goes back to
searching for a one to zero transition at the RXD input.
Please note that the value of the received stop bit is
unrelated to SBUF, RB8 or RI.
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相關代理商/技術參數 |
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| VRS550-PLC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
| VRS550-PLI25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
| VRS550-QAC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
| VRS550-QAI25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
| VRS550-QLC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU |
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