
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
18
Serial Port
The serial port included in the VRS550 and VRS560
can operate in full duplex; in other words, it can
transmit and receive data simultaneously. This occurs
at the same speed if one timer is assigned as the clock
source for both transmission and reception, and at
different speeds if transmission and reception are each
controlled by their own timer.
The serial port receive is buffered, which means that it
can begin reception of a byte even if the one previously
received byte has not been retrieved from the receive
register by the processor. However, if the first byte has
still not been read by the time reception of the second
byte is complete, the byte present in the receive buffer
will be lost.
One SFR register, SBUF, gives access to the transmit
and receive registers of the serial port. When users
read from the SBUF register, they will access the
receive register. When users write to the SBUF, the
transmit register will be loaded.
Serial Port Control Register
The serial port control register and status register
SCON contain the 9
th
data bit for transmit and receive
(TB8 and RB8) and all the mode selection bits. SCON
also contains the serial port interrupt bits (TI and RI).
T
ABLE
16:
S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(SCON) – SFR 98
H
7
6
5
SM0
SM1
SM2
Bit
Mnemonic
Description
7
SM0
Bit to select mode of operation (see table
below)
6
SM1
Bit to select mode of operation (see table
below)
5
SM2
Multiprocessor communication is possible
in modes 2 and 3.
In modes 2 or 3 if SM2 is set to 1, RI will
not be activated if the received 9
th
data bit
(RB8) is 0.
In Mode 1, if SM2 = 1 then RI will not be
activated if a valid stop bit was not
received.
4
REN
Serial Reception Enable Bit
This bit must be set by software and
cleared by software.
1: Serial reception enabled
0: Serial reception disabled
4
3
2
1
TI
0
RI
REN
TB8
RB8
3
TB8
9
th
data bit transmitted in modes 2 and 3
This bit must be set by software and
cleared by software.
9
data bit received in modes 2 and 3.
In Mode 1, if SM2 = 0, RB8 is the stop bit
that was received.
In Mode 0, this bit is not used.
This bit must be cleared by software.
Transmission Interrupt flag.
Automatically set to 1 when:
The 8
th
bit has been sent in Mode 0.
Automatically set to 1 when the stop bit
has been sent in the other modes.
This bit must be cleared by software.
Reception Interrupt flag
Automatically set to 1 when:
The 8
th
bit has been received in Mode 0.
Automatically set to 1 when the stop bit
has been sent in the other modes (see
SM2 exception).
This bit must be cleared by software.
2
RB8
1
TI
0
RI
T
ABLE
17:
S
ERIAL
P
ORT
M
ODES OF
O
PERATION
SM0
SM1
0
0
0
1
1
0
Mode
0
1
2
Description
Shift Register
8-bit UART
9-bit UART
Baud Rate
F
osc
/12
Variable
F
osc
/64
F
osc
/32
Variable
or
1
1
3
9-bit UART
Modes of Operation
The VRS550 / VRS560 devices serial port can operate
in four different modes. In all four modes, a
transmission is initiated by an instruction that uses the
SBUF SFR as a destination register. In Mode 0,
reception is initiated by setting RI to 0 and REN to 1.
An incoming start bit initiates reception in the other
modes provided that REN is set to 1. The following
paragraphs describe the four modes.