參數(shù)資料
型號(hào): VNC1L-1A
廠商: Future Technology Devices International Ltd
元件分類: 總線控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, GREEN, LQFP-48
文件頁數(shù): 9/32頁
文件大小: 672K
代理商: VNC1L-1A
Copyright 2009 Future Technology Devices International Limited
17
Document Reference No.: FT_000030
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.02
Clearance No.: FTDI# 50
Figure 5.3 SPI Slave Mode Timing
Time
Description
Minimum
Typical
Maximum
Unit
T1
SCLK Period
83
-
ns
T2
SCLK High
20
-
ns
T3
SCLK Low
20
-
ns
T4
Input Setup Time
10
-
ns
T5
Input Hold Time
10
-
ns
T6
Output Hold Time
2
-
ns
T7
Output Valid Time
-
20
ns
Table 5.5 SPI Slave Data Timing
5.2.2 SPI Master Data Read Transaction
The SPI master must periodically poll for new data in VNC1L Transmit Buffer. It is recommended that
this is done first before sending any command.
The Start and Setup sequence is sent to VNC1L by the SPI master, see Figure 5.4.
The VNC1L clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by
the SPI master. This is followed by a status bit generated by VNC1L. The Data Read status bit is defined
If the status bit indicates New Data then the byte received is valid. If it indicates Old Data then the
Transmit Buffer in VNC1L is empty and the byte of data received in the current transaction should be
disregarded.
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