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參數(shù)資料
| 型號(hào)： | VMS115 |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 58/64頁 |
| 文件大?。?/td> | 572K |
| 代理商： | VMS115 |
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VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
61
Revision: 2.3
906
Data Sheet
9 Pinout
The VMS115 is packaged in a 100 MQFP package.
VMS115 100 MQFP Pinout
Pin Name
Pin #
Type
Description
System Interface
CLK
89
IT
System Clock: This input is the master clock input used to derive
all internal clock signals.
RESET_L
31
ITS
Reset (active low): This input is the global reset signal that will
trigger and entire chip reset. This signal can be asserted asyn-
chronous to CLK. The signal must be asserted for one CLK
period to ensure exit of the reset state.
INT
40
OC
Interrupt (active high): Indicates that any enabled interrupt is
pending.
ZZ
83
IT
Sleep: This input is used to put the part in a sleep mode. In sleep
mode the chip operates in a reduced power consumption mode.
SSRAM Interface
CE_L
97
IT
Chip Enable (active low): Must be asserted for all data transfers
to the VMS115 chip. The VMS115 will ignore all bus activity
when CE_L is not asserted.
CMD[2:0]
87,86,85
IT
Command: These inputs are used to communicate the command
to the chip.
00x - Read register space
010 - Read Packet Data.
011 - Read context.
10x - Write register space
110 - Write packet data.
111 - Write context
A[10:0]
44,81,82,
99,100,
32,33,34,
35,37,38
IT
Address: Register address of memory location that is written or
read.
DQ[31:0]
29,28,26,
25,23,22,
20,18,16,
14,12,10,
8,6,4,2,
79,77,75,
73,71,69,
67,65,63,
61,59,57,
56,54,53,
51
IT/OC
Data In/Out: Bi directional data bus for moving data in/out of the
VMS115 chip.
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