參數(shù)資料
型號(hào)： VMS115
元件分類： 加密電路
英文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100
封裝： MQFP-100
文件頁(yè)數(shù)： 25/64頁(yè)
文件大?。?/td> 572K
代理商： VMS115
VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
31
Revision: 2.3
906
Data Sheet
5.3.5
Data Format
The data format into and out of the VMS115 chip is little endian. The data will be switched to big
endian for storage internally to the chip. All of the register accesses will be little endian access
(since there are no byte enables, the bit placement is the only information that has bearing).
Data Format (Endianess) Diagram
5.3.5.1
Data Format Examples and Test Cases
The following test cases represent the data format of data into and out of the VMS115 chip.
These test cases simulate realistic operations that the VMS115 chip may perform and provide the
input and output data in its proper format. The test cases provided are:
1. Encrypt - ECB - DES
2. Encrypt - CBC- DES
3. Encrypt - CBC - 3DES
4. Decrypt - CBC - 3DES
5. Hash - SHA-1
6. Hash - MD5
3
2
1
0
7
6
5
4
11
10
9
8
0
1
2
3
4
5
6
7
8
9
10
11
12
SSRAM Interface into VMS115
Internal Memory and IPSec Processor
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
00
01
02
03
00
01
02
03
h
g
f
e
d
c
b
a
h
g
f
e
d
c
b
a
031
31
0
Bit ‘a(chǎn)’ is the first bit received within the byte. The data will be stored in the Hash Block of the IPSec
Processor in the same format as the internal memory. The MD5 (little) and SHA-1 (big) algorthim will
process the data according to the hash specification for endianness.
DES operation on bytes 5 to 12 will generate a word per the
FIPS DES specfication
5
6
7
8
9
10
11
12
Word 01 Bits 8:31
DES Bits 1:24
Word 02 Bits 0:31
DES Bits 25:57
Word 03 Bits 0:7
DES Bits 58:64
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