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VCT 38xxA
ADVANCE INFORMATION
30
Micronas
Fig. 2–24:
Deflection processing block diagram
2.12.4.Vertical and East/West Deflection
The calculations of the vertical and East/West deflec-
tion waveforms is done by the internal Fast Processor
(FP). The algorithm uses a chain of accumulators to
generate the required polynomial waveforms. To pro-
duce the deflection waveforms, the accumulators are
initialized at the beginning of each field. The initializa-
tion values must be computed by the TV control pro-
cessor and are written to the front-end once. The
waveforms are described as polynomials in x, where x
varies from 0 to 1 for one field.
P: a
+
b
(x-0.5) +
c
(x-0.5)
2
+
d
(x-0.5)
3
+
e
(x-0.5)
4
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East/West deflection
are 12-bit values.
Fig. 2–25 shows several vertical and East/West deflec-
tion waveforms. The polynomial coefficients are also
stated.
In order to get a faster vertical retrace timing, the out-
put impedance of the vertical D/A-converter can be
reduced by 50 % during the retrace.
2.12.5.EHT Compensation
The vertical waveform can be scaled according to the
average beam current. This is used to compensate the
effects of electric high-tension changes due to beam
current variations. EHT compensation for East/West
deflection is done with an offset corresponding to the
average beam current.
Phase
Comparator
&
Low-pass
PLL2
E/W
correction
Sawtooth
PWM
15-bit
EW
VERT
VPROT
PWM
15-bit
DCO
Front
Sync
Interface
FSY
VDATA
Main
Sync
Generator
Vertical
Data
Phase
Comparator
&
Low-pass
PLL3
1:64
&
Output
Stage
HFLB
HOUT
DCO
Display
Timing
Line
Counter
blanking, clamping, etc.
Clock & Control
Sinewave
Generator
&
DAC
LPF
MSY
vertical reset
Skew
Measure-
ment
Angle &
Bow
+
VERTQ
Sync
Generation
INTLC