參數(shù)資料
型號(hào)： VCT3801A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video/Controller/Teletext IC Family
中文描述： 視頻/控制/圖文電視IC系列
文件頁數(shù)： 107/172頁
文件大?。?/td> 2243K
代理商： VCT3801A
ADVANCE INFORMATION
VCT 38xxA
Micronas
107
5.11.Memory Patch Module
The Memory Patch Module allows the user to modify
up to ten hard-wired ROM locations by external
means. This function is useful if faulty parts of software
or data are detected after the ROM code has been
cast into mask ROM.
Software loads addresses and the corrected code e.g.
from external non-volatile memory into respective
registers of the module. The module then will replace
faulty code upon address match.
Single ROM locations are directly replaced. Longer
faulty sequences may be repaired by introducing a
jump to a new subroutine in RAM (e.g. opcode JSR
requires 3 consecutive bytes to be patched). The RAM
subroutine then may consist of any number of instruc-
tions, ending with a return to the next correct instruc-
tion in ROM. In such a way it is possible to include also
complex software modules.
5.11.1.Features
– patching of read data from up to 10 different ROM
locations (24 bit physical address)
– automatic insertion of 1 CPU wait state for each
patched access
Fig. 5–16:
Block diagram of patch module
5.11.2.General
The logic contains ten patch cells (see Fig. 5–16 on
page 107), each consisting of a 24-bit compare regis-
ter (Patch Address register, PARn), a 24-bit address
comparator, a Patch Enable register (PERn) bit and an
8-bit Patch Data register (PDR).
The current address information for a ROM access is
fed to a bank of ten patch cells. In case of a match in
one patch cell, and provided that the corresponding
Patch Enable register bit is set, a wait cycle for CPU is
included by pulling down the RDY input of CPU for one
cycle (see Fig. on page 108). In the meantime the
module’s logic disables the ROM data bus drivers and
instead places the data information from the corre-
sponding Patch Data register on the data bus.
5.11.3.Initialization
After reset, as bit PER0.PMEN is reset to 0, all patch
cell registers are in Write mode and patch operation is
disabled.
To initialize a patch cell, first set the corresponding
PSEL bit in register PER0 or PER1 as a pointer. Then
enter the 24bit address to registers PAR2 (High byte),
PAR1 (middle byte) and PAR0 (Low byte) and the
desired patch code to register PDR.
If desired, repeat the above sequence for other patch
cells. Only set one PSEL pointer bit in registers PER0
and PER1 at a time.
PA[23:16]
PA[7:0]
ADB[23:0]
DB[7:0]
≥
1
PA[15:8]
Patch Address Register
P
Output Enable
Patch Data
Patch Cell 0
Patch Cells 1...9
Register
Enable
Write/Compare
Sequencer
P
P
DBP[7:0]
RDY
ROMEN
RWQ
ROMACC
PH2
PATOE
&
≡
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