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參數(shù)資料
| 型號(hào)： | V96BMC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS |
| 中文描述： | 爆高性能的DRAM控制器的i960Cx/Hx/Jx處理器 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | V96BMC |
V96BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V96BMC Rev D Data Sheet Rev 3.2
3
Table 3: Signal Descriptions
Memory Interface Signals
Signal
Type
R
a
Description
AA[11:0]
AB[11:0]
O
12-3
X
Leaf A and B row and column address, multiplexed on the same
pins. When non-interleaved operation is selected, only address bus
AA should be used.
RASA[3:0]
RASB[3:0]
O
12-3
H
Row Address Strobe. These strobes indicate the presence of a valid
row address on busses AA(B)[11:0]. These signals are to be con-
nected one to each 32-bit leaf of memory.
CASA[3:0]
CASB[3:0]
O
12-3
H
Column Address Strobe. These strobes latch a column address from
AA(B)[11:0]. They are assigned one to each byte in a leaf.
MWEA
MWEB
O
12-3
H
Memory Write Enable. These are the DRAM write strobes. One is
supplied for each leaf to minimize signal loading.
RFS/AUXT
O
12
H
Refresh in progress. This output is multi-function signal. The signal
name, as it appears on the logic symbol, is the default signal names.
This signal gives notice that a refresh cycle is to be executed. The
timing leads RAS only refresh by one cycle. The output may also
function as AUX timer interrupt.
Configuration
Signal
Type
R
Description
HMODE
I
Connected to Vcc (for i960Cx) or GND (for i960Hx/Jx).
Buffer Controls Signals
Signal
Type
R
Description
TXA
TXB
O
12
H
Data Transmit A and B. These outputs are multi-function signals.
The signal names, as they appear on the logic symbol, are the
default signal names (Mode 0). The purpose of these outputs is to
control buffer output enables during data read transactions and, in
effect, control the multiplexing of data from each memory leaf onto
the i960Cx/Hx/Jx data bus.
These outputs are mode independent, however, the timing of the
signals change for different operational modes. They control trans-
parent latches that hold data transmitted during a write transaction.
In modes 0 and 1, the latch controls follow the timing of CAS for
each leaf, while in modes 2 and 3 the timing of LEA and LEB is
shortened to 1/2 clock.
LEA
LEB
O
12
L
Local Bus Interface
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