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| 型號(hào)： | V96BMC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS |
| 中文描述： | 爆高性能的DRAM控制器的i960Cx/Hx/Jx處理器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | V96BMC |
V96BMC Rev.D
10
V96BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
4.0 AC Specifications
1. For 3.3 Volt DRAM intreface operation.( See also note 8 table 11)
Table 8: DC Operating Specifications Vcc3=3.3 Volt and Vcc=5 Volt
Symbol
Description
Conditions
Min
Max
Units
V
OL
Low level output voltage
V
IN
= Vcc3
I
OL
= 12 mA
0.4
V
V
OH
High level output voltage
V
IN
= Vcc3
I
OL
= -12 mA
2.4
V
I
OZL
Low level float input
leakage
V
IN
= Vcc2
V
O
= GND
-10
μ
A
I
OZH
High level float input
leakage
V
IN
= V
IL
or
V
IH
V
O
=4.46V
10
μ
A
I
CC
(max)
Maximum supply current
Continuous simple access
Continuous burst access
140
40
mA
Table 9: AC Test Conditions
Symbol
Parameter
Limits
Units
Vcc3/Vcc
Supply voltage
4.75 to 5.25
V
V
CC3
Supply voltage when 3.3 Volt DRAM inter-
face operation
1
(Vcc is still as above)
3.0 to 3.6
V
V
IN
Input low and high voltages
0.4 and 4.25
V
C
OUT
Capacitive load on output and I/O pins
50
pF
Table 10: Capacitive Derating for Output and I/O Pins
Output Drive Limit
Supply voltage
Derating
12 mA
Vcc=5 Volt, Vcc3=3.3 Volt
0.06 ns/pF for loads > 50 pF
12 mA
Vcc=5 Volt, Vcc3=5 Volt
0.04 ns/pF for loads > 50 pF
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