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參數(shù)資料
| 型號： | V96BMC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS |
| 中文描述： | 爆高性能的DRAM控制器的i960Cx/Hx/Jx處理器 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | V96BMC |
V96BMC Rev.D
12
V96BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
NOTES:
1. Specified from PCLK falling edge.
2. t
M
= t
C
when T_MUX = 1; t
M
= 0.5
t
C
when T_MUX = 0.
3. Maximum RAS pulse width depends on the number of burst access.
4. t
N
= 1.5
t
C
when T_RAS = 0; t
N
= 2.5
t
C
when T_RAS = 1.
5. t
P
= 2
t
C
when T_RAS = 0; t
P
= 2
t
C
when T_RAS = 1 and T_RP = 1;
t
P
= 3
t
C
when T_RAS = 1 and T_RP = 0.
6. Rising delay is measured from PCLK falling edge, falling delay is measured from PCLK rising edge.
7. Except for Mode 2 and 3 at TXA pin.
8. In order to have 3.3 Volt DRAM interface Vcc3 pins must be connected to 3.3 Volt.
Vcc3 pins are: PIN # 91, 97, 103, 109, 57, 63, 69, 75, 81.
The power supply pins that must always be connected to 5V are Vcc.
Vcc pins are: PIN # 4, 47, 115.
Figure 3: Clock and Synchronous Signals
t
WEH
t
LED
t
TXHL1
t
TXHL2
Write Enable hold from RAS de-assertion
1
3
1
3
ns
PCLK to Latch Enable output delay
6
3
12
3
10
ns
PCLK to Buffer Control fall delay
7
3
13
3
11
ns
PCLK to Buffer Control fall delay (Mode 2 and
3 at TXA pin only)
4
15
4
13
ns
t
TXLH
t
RFHL
t
RFLH
t
ASU
t
AH
PCLK to Buffer Control rise delay
3
12
3
10
ns
REFRESH synchronous assertion delay
3
13
3
11
ns
REFRESH synchronous de-assertion delay
3
13
3
11
ns
Address setup to ALE Falling
6
5
ns
Address hold from ALE Falling
5
4
ns
Table 11: Timing Parameters for V96BMC Vcc=5 Volts +/- 5% and Vcc3= 5 or
3.3
8
Volts +/- 5%
LOCAL CLOCK
INPUT SETUP/HOLD
OUTPUT FALLING DELAY
OUTPUT RISING DELAY
OUTPUT RISING DELAY
VALID
t
C
t
CH
t
CL
t
H
t
SU
t
LED, BH,
RFHL, TXHL1, TXHL2
t
BLH, ETXLH
t
LED
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