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參數(shù)資料
| 型號： | V91F564U24QBFW-F5 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大小： | 196K |
| 代理商： | V91F564U24QBFW-F5 |
V91F564U24QB Rev 1.0 July 2006
13
V91F564U24QB
ProMOS TECHNOLOGIES
Reference Clock Input Specifications
Notes :
1.133MHz for PC2-4200 and 166MHz for PC2-5300.
2. Measured with SSC disabled.
3. Measured differentially through the range of 0.175V to 0.525V.
4. The crossing point must meet the absolute and relative crossing point specification simultaneously.
5. VCROSS_REL_(MIN) and VCROSS_REL(MAX) are derived using the following calculation : Min = 0.5(Vhavg-0.710)+0.250;and
Max=0.5(Vhavg-0.710)+0.550, where Vhavg is the average of VSCK-HIGHM.
6. Measured with a single-ended input voltage of 1V.
7. Applies to reference clocks SCK and SCK.
8. Difference between SCK and SCK input.
9. T1 = [Tdatapath-Tclockpath](excluding PLL loop delays). This parameter is not a direct clock output parameter but in indirectly deter-
mines the clock output parameter TREF-JITTER.
10. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the
reference clock source, through the TX, to data arrival at the data dampling point in the RX. The clock path is defined from the reference
clock source to clock arrival at the same sampling point. The path delays are caused by copper trace routes. on-chip routing, on-chip
buffering, etc. They include the time-of flight of interpolators or other clock adjustment mechanisms. They do not include the phase
delays caused by finite PLL loop bandwidth because these delays are modeled by the PLL transfer functions.
11. Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured over a small-
er, yet statistically significant, sample size and the total jitter at 1016 samples extrapolated from an estimate of the sigma of the random
jitter components.
12. Measured with SSC enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRXTotal - MIN
parameters
Parameter
Symbol
Values
Units
Note
MIN
MAX
Reference clock frequency
fsck
133
200
MHz
1.2
Rise time, fall time
TSCK-RISE, TSCK-FALL
175
700
ps
3
Voltage high
VSCK-HIGH
660
850
mV
Voltage low
VSCK-LOW
-150
mV
Absolute crossing point
VCROSS-ABS
250
550
mV
4
Relative crossing
VCROSS-REL
calculated
4,5
Percent mismatch between rise and
fall times
TSCK-RISE-FALL-MATCH
-10
%
Duty cycle of reference clock
TSCK-DUTYCYCLE
40
60
%
Clock leakage current
II-CK
-10
10
uA
6,7
Clock input capacitance
CI-CK
0.5
2
pF
7
Clock input capacitance delta
CI_CK(D)
-0.25
0.25
pF
8
Transport delay
T1
5
ns
9, 10
Phase jitter sample size
NSAMPLE
1016
Periods
11
Reference clock jitter, filtered
TREF-JITTER
40
ps
12,13
Reference clock deterministic jitter
TREF-DJ
TBD
ps
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