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參數(shù)資料
| 型號： | V91F564U24QBFW-F5 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 196K |
| 代理商： | V91F564U24QBFW-F5 |
V91F564U24QB Rev 1.0 July 2006
8
V91F564U24QB
ProMOS TECHNOLOGIES
High-Speed Differential Point-to-Pint Link (at 1.5V) interfaces
The Advanced Memory Buffer supports one FBDIMM Channel consisting of two bidirectional link interfaces
using highs peed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide
and carries commands and write data from the host memory controller or the adjacent DIMM in the host
direction. The southbound output link forwards this same data to the next FBDIMM. The north-bound input
link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain
back towards the host. The northbound output link forwards this information back towards the host and mul-
tiplexers in any read return data or status information that is generated internally. Data and commands sent
to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs
and status information travel northbound on 14 primary differential pairs. Data and commands sent to the
adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs.
Data and status information received from the adjacent DIMM upstream travel further northbound on 14 sec-
ondary differential pairs.
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The
DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit
signals. There are two copies of address and command signals to support DIMM routing and electrical re-
quirements. Four transfer bursts are driven on the data and check-bit lines at 800MHz. Propagation delays
between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by
hardware state machine using write/read trial and error. Hardware aligns the read data and check-bits to a
single core clock. The Advanced Memory Buffer provides four copies of the command clock phase referenc-
es(CLK[3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble.
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration regis-
ters independent of the FBDIMM link. The Advanced Memory Buffer will never be a master on the SMBus,
only a slave. Serial SMBus data transfer is supported at 100kHz. SMBus data transfer is supported at
100kHz. SMBus access to the Advanced Memory Buffer maybe a requirement to boot and to set link
strength, frequency and other parameters needed to insure robust configurations. It is also required for di-
agnostic support when the link is down. The SMBus address straps located on the DIMM connector are used
by the unique ID.
Channel Latency
FBDIMM channel latency is measured from the time a read request is driven on the FBDIMM channel pins
to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller.
When not using the variable read latency capability, the latency for a specific DIMM on a channel is always
equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in a specific
configuration with some number of DIMMs installed may not be equal
Peak Theoretical Throughput
An FBDIMM channel transfers read completion data on the FBDIMM Northbound data connection. 144 bits
of data are transferred for every FBDIMM Northbound data frame. This matches the 18 byte data transfer
of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 from a single channel or a
DRAM burst of four from to lock-stepped channels provides a total of 72 bytes of data (64 bytes plus 8 bytes
ECC).
The FBDIMM frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the channel
clock to the DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak
theoretical throughput as a single DRAM channel. For example, when using the DDR2 533 DRAMs, the
peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec. Write data is transferred on
the Southbound command and data connection, via Command+Wdata frames. 72 bits of data are trans-
ferred for every Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of
an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers from a single channel,
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