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參數資料
| 型號： | V826632M24SAIW-D3 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.65 ns, ZMA172 |
| 封裝： | GREEN, MICRO, DIMM-172 |
| 文件頁數： | 2/14頁 |
| 文件大?。?/td> | 161K |
| 代理商： | V826632M24SAIW-D3 |
10
V826632M24SA Rev. 1.3 April 2006
ProMOS TECHNOLOGIES
V826632M24SA
AC Characteristics (AC operating conditions unless otherwise noted)
Parameter
Sym-
bol
(PC400A)
D0
(PC400B)
D3
(PC333)
C0
(PC266A)
B1
(PC266B)
B0
Units
Note
Min
Max Min
Max
Min
Max
Row Cycle Time
tRC
60
-
60
-
60
-
65
-
65
-
ns
Auto Refresh Row Cycle Time
tRFC
70
-
70
-
72
-
75
-
75
-
ns
Row Active Time
tRAS
40
120K
40
120K
42
120K
45
120K
45
120K
ns
Row Address to Column Address
Delay
tRCD
15
-
15
-
18
-
15
-
20
-
ns
Row Active to Row Active Delay
tRRD
10
-
10
-
12
-
15
-
15
-
ns
Column Address to Column Ad-
dress Delay
tCCD
1
-
1
-
1
-
1
-
1
-
tCK
Row Precharge Time
tRP
15
-
15
-
18
-
15
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Last Data-In to Read Command
tDRL
1
-
1
-
1
-
1
-
1
-
tCK
Auto Precharge Write Recovery +
Precharge Time
tDAL
35
-
35
-
35
-
35
-
35
-
ns
System Clock
Cycle Time
CAS Latency = 3
tCK
5
12
5
12
-
12
-
12
-
12
ns
CAS Latency = 2.5
5
12
6
12
6
12
7
12
7.5
12
ns
CAS Latency = 2
7.5
12
7.5
12
7.5
12
7.5
12
10
12
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Data-Out edge to Clock edge Skew
tAC
-0.65
0.65
-0.65
0.65
-0.75
0.75
-0.75
0.75
-0.75
0.75
tCK
DQS-Out edge to Clock edge Skew tDQSCK -0.60
0.60
-0.60
0.60
-0.75
0.75
-0.75
0.75
-0.75
0.75
tCK
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.40
-
0.40
-
0.45
-
0.5
-
0.5
tCK
Data-Out hold time from DQS
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tCK
1
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCK
1
Input Setup Time (fast slew rate)
tIS
0.6
-
0.6
-
0.75
-
0.9
-
0.9
-
tCK
2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.6
-
0.6
-
0.75
-
0.9
-
0.9
-
tCK
2,3,5,6
Input Setup Time (slow slew rate)
tIS
0.75
-
0.75
-
0.8
-
1.0
-
1.0
-
tCK
2,4,5,6
Input Hold Time (slow slew rate)
tIH
0.75
-
0.75
-
0.8
-
1.0
-
1.0
-
tCK
2,4,5,6
Input Pulse Width
tIPW
0.4
0.6
0.4
0.6
0.4
0.6
2.2
-
2.2
-
tCK
6
Write DQS High Level Width
tDQSH
0.35
tCK
Write DQS Low Level Width
tDQSL
0.35
tCK
CLK to First Rising edge of DQS-In tDQSS
0.72
1.25
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
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相關代理商/技術參數 |
參數描述 |
|---|---|
| V826664G24S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:512 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 64M x 64 |
| V826664K24S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 64M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE |
| V827316K04S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 16M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V827332K04S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V827332N04S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
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