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參數(shù)資料
| 型號： | V62C3184096L-55T |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP-32 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 52K |
| 代理商： | V62C3184096L-55T |
MOSEL V ITELIC
V62C3184096
5
V62C3184096 Rev. 1.1 June 2000
Data Retention Characteristics
NOTES:
1.
2.
t
RC
= Read Cycle Time
T
A
= +25
°
C.
Low V
CC
Data Retention Waveform (1) (CE
1
Controlled)
Key to Switching Waveforms
Symbol
Parameter
Power
Min.
Typ.
(2)
Max.
Units
V
DR
V
CC
for Data Retention
CE
1
≥
V
CC
–
0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
–
0.2V,
or V
IN
≤
0.2V
2.0
—
3.3
V
I
CCDR
Data Retention Current
CE
1
≥
V
DR
–
0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
–
0.2V,
or V
IN
≤
0.2V, V
DR
= 2.0V
Com
’
l
L
—
1
4
μ
A
LL
—
0.5
3
Ind.
L
—
—
7
LL
—
—
5
t
CDR
Chip Deselect to Data Retention Time
0
—
—
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC(1)
—
—
ns
V
CC
Data Retention Mode
CE
1
≥
V
CC
–
0.2V
CE
1
2.2V
2.2V
2.7V
t
CDR
t
R
V
DR
≥
2V
2.7V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“
OFF
”
STATE
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