參數(shù)資料
型號(hào)： V58C2128164SBLS7
廠商： PROMOS TECHNOLOGIES INC
元件分類(lèi)： DRAM
英文描述： 8M X 16 DDR DRAM, 0.75 ns, PBGA60
封裝： MO-233, FBGA-60
文件頁(yè)數(shù)： 21/62頁(yè)
文件大?。?/td> 977K
代理商： V58C2128164SBLS7
28
V58C2128(804/404/164)SB Rev. 1.1 March 2004
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SB
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Note
H
X
LLLL
OP code
1,2
H
X
LLLL
1,2
Device Deselect
HX
H
XXX
X1
No
L
H
Bank Active
H
X
L
H
RA
V
1
Read
H
X
LHLH
CA
L
V
1
Read with Autoprecharge
H1,3
Write
HX
L
H
L
CA
L
V
1
Write with Autoprecharge
H1,4
Precharge All Banks
HX
L
H
L
X
HX
1,5
Precharge selected Bank
LV
1
Read Burst Stop
H
X
L
H
L
X
1
Auto
H
LLL
H
X
1
Self Refresh
Entry
H
L
LLL
H
X
1
Exit
L
H
XXX
1
L
HHH
Precharge Power
Down Mode
Entry
H
L
H
XXX
X
1
L
HHH
1
Exit
L
H
XXX
1
L
HHH
1
Active Power
Down Mode
Entry
H
L
H
XXX
X
1
L
VVV
1
Exit
L
H
X
1
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
OP code
Refresh
Operation
Mode Register Set
Extended Mode Register Set
DDR SDRAM SIMPLIFIED COMMAND TRUTH TABLE
相關(guān)PDF資料
PDF描述
V58C2128404SCLJ5 32M X 4 DDR DRAM, 0.65 ns, PBGA60
V58C2256324SAH-36 8M X 32 DDR DRAM, 0.55 ns, PBGA144
V58C2256404SBJ5 64M X 4 DDR DRAM, 0.65 ns, PBGA60
V58C2256164SBLJ5B 16M X 16 DDR DRAM, 0.65 ns, PBGA60
V58C2256404SCLS7I 64M X 4 DDR DRAM, 0.75 ns, PBGA60
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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V58C2256164S 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM
V58C2256324SAB30 制造商:Marvell 功能描述:Marvell V58C2256324SAB30
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