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參數(shù)資料
| 型號： | V58C2128164S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| 中文描述： | 高性能2.5伏128兆位DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 1/59頁 |
| 文件大?。?/td> | 948K |
| 代理商： | V58C2128164S |
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MOSEL VITELIC
1
V58C2128(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
PRELIMINARY
V58C2128(804/404/164)S Rev.1.6 March 2002
6
7
75
8
DDR333B
DDR266A
DDR266B
DDR200
Clock Cycle Time (t
CK2
)
7.5 ns
7.5ns
10 ns
10 ns
Clock Cycle Time (t
CK2.5
)
6 ns
7ns
7.5 ns
8 ns
System Frequency (f
CK max
)
167 MHz
143 MHz
133 MHz
125 MHz
Features
■
High speed data transfer rates with system
frequency up to 166 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 4096 cycles/64 ms
■
Available in 66-pin 400 mil TSOP
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V
■
QFC options for FET control. x4 parts.
*
Note:
DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-3-3 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2128(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
-6
-7
-75
-8
Std.
L
0°C to 70°C
Blank
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C2128404S | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128804S | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C265164S | 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| V58C265804S | HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C2128404S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2256 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256324SAB30 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB30 |
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