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參數(shù)資料
| 型號： | V55C2256164VGLK-10H |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封裝： | 8 X 10 MM, GREEN, MO-210, FBGA-54 |
| 文件頁數(shù)： | 2/47頁 |
| 文件大?。?/td> | 581K |
| 代理商： | V55C2256164VGLK-10H |
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ProMOS TECHNOLOGIES
V55C2256164VG
10
V55C2256164VG Rev. 1.0 September 2008
Burst Length and Sequence:
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one tRC delay
is required prior to any access command.
.
a data mask function for writes. When DQM is
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2
Not supported
The Deep Power Down mode is an unique functi
on with very low standby currents. All internal volat
ge generators inside the RAM are stopped and all
Deep Power Down Mode
memory data is lost in this mode. To enter the Deep
Power Down mode all banks must be precharged.
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