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參數(shù)資料
| 型號： | V54C365164VCT8PC |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 54/54頁 |
| 文件大小： | 1570K |
| 代理商： | V54C365164VCT8PC |
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V54C365164VC Rev. 0.8 July 2001
MOSEL VITELIC
V54C365164VC
operation. If CA10 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3
and three clocks for CAS latencies 4. If CAS10 is
high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to tWR (Write recovery time)
after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge oper-
ation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list.
The precharge command can be imposed one clock
before the last data out for CAS latency = 2, two
clocks before the last data out for CAS latency = 3
and three clocks before the last data out for CAS la-
tency= 4. Writes require a time delay twr from the
last data out to apply the precharge command.
Bank Selection by Address Bits:
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate
the
burst
operation
prematurely.
These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write Com-
mand care must be taken to avoid I/O contention.
The Burst Stop Command, however, has the fewest
restrictions making it the easiest method to use
when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual data
from the burst write cycle will be ignored. Data that
is presented on the I/O pins before the Burst Stop
Command is registered will be written to the
memory.
A10
BA0
BA1
0
Bank 0
0
1
Bank 1
0
1
0
Bank 2
0
1
Bank 3
1
X
all Banks
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| V54C365164VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 |
| V54C365324V | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 2M X 32 SDRAM 4 BANKS X 512Kbit X 32 |
| V54C365404VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4 |
| V54C365804VC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
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