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參數(shù)資料
| 型號(hào)： | V54C365164VCT8PC |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 34/54頁 |
| 文件大小： | 1570K |
| 代理商： | V54C365164VCT8PC |
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4
V54C365164VC Rev. 0.8 July 2001
MOSEL VITELIC
V54C365164VC
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
4M x 16 SDRAM CA0–CA7
(Page Length = 256 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
LDQM and UDQM controls the lower and upper bytes in a x16 SDRAMs.
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
——
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C365164VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 |
| V54C365324V | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 2M X 32 SDRAM 4 BANKS X 512Kbit X 32 |
| V54C365404VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4 |
| V54C365804VC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
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