- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202172 > V54C3256804VBS7 (PROMOS TECHNOLOGIES INC) 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | V54C3256804VBS7 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | MO-210, FBGA-60 |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 728K |
| 代理商： | V54C3256804VBS7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
18
V54C3256(16/80/40)4VB Rev. 1.0 December 2003
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VB
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1.
4.
If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5.
If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
Read Cycle
21
tOH
Data Out Hold Time
3
–
3
–
3
–3–ns
2
22
tLZ
Data Out to Low Impedance Time
1
–
1
–
1
–0–ns
23
tHZ
Data Out to High Impedance Time
3
6
3
7
3
738ns
7
24
tDQZ
DQM Data Out Disable Latency
–
2
–
2
–
2
–
2
CLK
Write Cycle
25
tWR
Write Recovery Time
2–
2
–
CLK
26
tDQW
DQM Write Mask Latency
0
–
0
–
0
–
0
–
CLK
#
Symbol
Parameter
Limit Values
Unit
Note
-6
-7PC
-7
-8PC
Min. Max. Min. Max. Min. Max. Min. Max.
1.4V
tCS
tCH
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
tT
Figure 1.
tCK
AC Characteristics (Cont’d)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V54C365164VCT8PC | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| V55C2256164VBT10I | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| V55C3256164VGLK-10IPC | SYNCHRONOUS DRAM, PBGA54 |
| V55C3256164VGLK-7HPC | SYNCHRONOUS DRAM, PBGA54 |
| V580MC04 | VCO, 850 MHz - 890 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3256804VBT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C328404VCT7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| V54C328404VCT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。