參數(shù)資料
型號： V54C3128804VAS7PC
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： SOC-60
文件頁數(shù)： 6/49頁
文件大小： 696K
代理商： V54C3128804VAS7PC
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
14
V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to tWR (Write recovery time)
after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
Burst Termination
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the
burst operation
prematurely.
These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
A10
BA0
BA1
0
Bank 0
0
1
Bank 1
0
1
0
Bank 2
0
1
Bank 3
1X
X
all Banks
Recommended Operation and Characteristics for LV-TTL
TA = 0 to 70 °C; VSS = 0 V; VCC,VCCQ = 3.3 V ± 0.3 V
Note:
1.
All voltages are referenced to VSS.
2.
VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 4.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 4.0 mA)
VOL
–0.4
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 5
5
A
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
– 5
5
A
相關(guān)PDF資料
PDF描述
V54C3128804VCLC7E 16M X 8 SYNCHRONOUS DRAM, 7 ns, PBGA54
V54C3128804VCT7PCE 16M X 8 SYNCHRONOUS DRAM, 7 ns, PDSO54
V54C316162VAT10 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50
V54C3256164VAT6 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
V54C3256404VDS8IPC 64M X 4 SYNCHRONOUS DRAM, 6 ns, PBGA60
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V54C3128804VAT 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8
V54C3128804VAT7 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8
V54C3128804VAT8 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8
V54C3128804VBGA 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, BGA PACKAGE
V54C3128804VBJ7IPC 制造商:Mosel Vitelic Corporation 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*