參數(shù)資料
型號(hào)： V54C3128804VAS7PC
廠商： MOSEL-VITELIC
元件分類(lèi)： DRAM
英文描述： 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： SOC-60
文件頁(yè)數(shù)： 46/49頁(yè)
文件大?。?/td> 696K
代理商： V54C3128804VAS7PC
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
6
V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
*
Note:Capacitance is sampled and not 100% tested.
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
Parameter
Max. Unit
CI1
Input Capacitance (A0 to A11)
3.8
pF
CI2
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
3.8
pF
CIO
Output Capacitance (I/O)
6
pF
CCLK
Input Capacitance (CLK)
3.5
pF
Block Diagram
Row decoder
Memory array
Bank 0
4096 x 512
x 16 bit
C
o
lu
mn
dec
oder
S
ens
e
ampl
if
ie
r&
I(
O
)bus
Row decoder
Memory array
Bank 1
4096 x 512
x16 bit
C
o
lu
mn
d
e
c
o
der
S
e
ns
e
ampl
if
ie
r&
I(
O
)
bus
Row decoder
Memory array
Bank 2
4096 x 512
x 16 bit
Co
lu
m
n
d
e
c
o
d
e
r
S
ens
e
ampl
if
ie
r&
I(
O
)bus
Row decoder
Memory array
Bank 3
4096 x 512
x 16 bit
Co
lu
m
n
d
e
c
o
d
e
r
S
ens
e
ampl
if
ie
r&
I
(O
)bus
Input buffer
Output buffer
I/O1-I/O16
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A11, BA0, BA1
A0 - A8, AP, BA0, BA1
Control logic & timing generator
CL
K
CK
E
CS
RA
S
CA
S
WE
LD
Q
M
Row Addresses
Column Addresses
UDQM
x16 Configuration
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