參數(shù)資料
型號(hào)： USB97CFDC-MN
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 存儲(chǔ)控制器/管理單元
英文描述： USB FLOPPY DISK CONTROLLER
中文描述： 1 Mbps, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： 12 X 12 MM, TQFP-100
文件頁(yè)數(shù)： 52/59頁(yè)
文件大?。?/td> 385K
代理商： USB97CFDC-MN
SMSC DS – USB97C201
Page 52
Rev. 03/25/2002
PRELIMINARY
RAMRD_
TOGGLE
Written
No
Yes
RAMRD_
TOGGLE=
0
No
Yes
RAMRD_A=0;
Begin
Output A Buffer
SRAM Data
RAMRD_
TOGGLE
Written
Yes
No
POR
RAMRD_A=1
RAMRD_B=1
Output
Completed
No
Yes
RAMRD_A=1
RAMRD_
TOGGLE=
0
Yes
No
RAMRD_B=0;
Begin
Output B Buffer
SRAM Data
RAMRD_
TOGGLE
Written
No
Output
Completed
No
Yes
RAMRD_B=1
RAMRD_
TOGGLE=
1
No
Yes
Yes
OUTPUT
FLOW CONTROL
ACTIVE
OUTPUT
FLOW CONTROL
INACTIVE
RAMRD_B=0
RAMRD_B=0
Yes
No
RAMRD_A=0
RAMRD_A=0
Yes
FIGURE 4 - TRANSMIT BUFFER OPERATION
Transmit buffer operations are always initiated by writing the RAMRD_TOGGLE bit in the EP2 Control register.
Output flow control to the device receiving data from the SRAM buffer is active once data in both buffers has been
transferred. If the destination is the SIE, then it will NYET or NAK further INs. If it is the ATA interface, nDAK will not
be asserted in response to DRQ data will not be clocked out.
6.9.3
If the AUTO_TRANS bit is set in the ATA_CTL register, then automatic manipulation of the RAMWR_TOGGLE,
RAMRD_TOGGLE, RAMWR_B, and RAMWR_A bits is executed by a state machine to allow continuous streaming
of the data between EP2 and the ATA DMA interface. Automatic transfer of byte counts between the
RAMWRBC_A/B and RAMRDBC_A/B registers is also implemented. This is illustrated in Figure 5.
AUTOMATIC TRANSFER OPERATION
Note
: If the count in RAMWRBC_A/B is zero, no transfer will occur. This is likely to happen on transfers from the SIE
to the ATA at the very end of the transfer.
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