參數(shù)資料
型號(hào)： USB97CFDC-MN
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： USB FLOPPY DISK CONTROLLER
中文描述： 1 Mbps, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： 12 X 12 MM, TQFP-100
文件頁(yè)數(shù)： 28/59頁(yè)
文件大?。?/td> 385K
代理商： USB97CFDC-MN
SMSC DS – USB97C201
Page 28
Rev. 03/25/2002
PRELIMINARY
Table 22 - Wakeup Source 1 Register (INT2)
WU_SRC_1
(0XA0 – RESET=0x00)
BIT
NAME
[7:3]
Reserved
2
USB_Reset
WAKEUP SOURCE 1
DESCRIPTION
R/W
R/W
R/W
Reserved
This bit is set when the SIE detects simultaneous logic lows on D+
and D- (Single-Ended 0) for 32 to 64 full speed bit times, or 4 to 8
low speed bit times (or 2.5<t<5.5us). The USB_Reset signal may be
as long as 10ms. SETUP tokens can be NAK'd for up to 10ms after
the Reset signal is released.
This bit is set on detection of Global Resume state (when there is a
transition from the "J" state while in Global Suspend).
This bit will be set if the ATA_IRQ bit of the ISR_0 register is set OR
if the 8051 INT4 signal (GPIO Interrupts) is high.
1
Resume
R/W
0
EXT_INT
R
Note 1:
The bits 1 and 2 in this register are cleared by writing a ‘1’ to the corresponding bit.
Note 2:
Unmasked Wakeup Source bits restart the 8051 when its clock is stopped. This restarts the Ring Oscillator
and crystal oscillator for the MCU to resume from <500μA operation.
Note 3:
To initiate USB Remote Wakeup, the SIE_Resume bit should be used in the SIE_CONF register.
Table 23 - Wakeup Mask 1 Register
WU_MSK_1 (Note 1)
(0XA6 - RESET=0xFF)
BIT
NAME
[7:3]
Reserved
2
USB_Reset
WAKEUP MASK 1
DESCRIPTION
R/W
R
R/W
This bit always reads “1”.
External wakeup event.
0 = Enabled
1 = Masked
External wakeup event.
0 = Enabled
1 = Masked
External wakeup event.
0 = Enabled
1 = Masked
1
Resume
R/W
0
EXT_INT
R/W
Note 1:
Interrupt events enabled by these bits are Ored and routed to the INT2 external interrupt input of the 8051
core.
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