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| 型號： | USB97CFDC-MN |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | USB FLOPPY DISK CONTROLLER |
| 中文描述： | 1 Mbps, FLOPPY DISK DRIVE CONTROLLER, PQFP100 |
| 封裝： | 12 X 12 MM, TQFP-100 |
| 文件頁數(shù)： | 31/59頁 |
| 文件大?。?/td> | 385K |
| 代理商： | USB97CFDC-MN |
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SMSC DS – USB97C201
Page 31
Rev. 03/25/2002
PRELIMINARY
Table 28 – SIE Status Register
SIE_STAT
(0xB0 - RESET=0x00)
NAME
SET_STALL
SIE STATUS REGISTER
DESCRIPTION
BIT
[7]
R/W
R/W
Set to “1” if a SET_FEATURE_ENDPOINT_HALT command
is received on any endpoint by the SIE. Which endpoint is
STALLed can be determined by examining their CTL
registers.
Set to “1” if a CLEAR_FEATURE_ENDPOINT_HALT
command is received on any endpoint by the SIE. Which
endpoint’s STALL condition is cleared can be determined
by examining their CTL registers.
Set to “1” if a SET_CONFIGURATION command is received
on endpoint 0 by the SIE and the resulting configuration is
set and reported in the USB_CONFIG register.
This read only bit always returns the value of “0”.
Set to “1” if a SET_INTERFACE command is received on
endpoint 0 by the SIE.
This read only bit always returns the value of “0”.
Set to “1” if a SET_FEATURE_REMOTE_WAKE_UP
command is received on endpoint 0 by the SIE.
Set
to
CLEAR_FEATURE_ENDPOINT_REMOTE_WAKE_UP
command is received on endpoint 0 by the SIE.
6
CLR_STALL
R/W
5
SET_CONF
R/W
4
3
Reserved
SET_INTF
R
R/W
2
1
Reserved
SET_REMWU
R-
R/W
0
CLR_REMWU
R/W
“1”
if
a
Note:
These bits are masked by the SIE_MSK register and OR’d to drive the INT3 interrupt line into the 8051 core.
They may be cleared writing a “1” to the bit location.
Table 29 – SIE Status Mask Register
SIE_MSK
(0xAE - RESET=0xFF)
NAME
SET_STALL
SIE STATUS MASK REGISTER
DESCRIPTION
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
This read only bit always returns the value of “1”.
1= Disable interrupt generation.
0= Enable interrupt generation.
This read only bit always returns the value of “1”.
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
BIT
[7]
R/W
R/W
6
CLR_STALL
R/W
5
SET_CONF
R/W
4
3
Reserved
SET_INTF
R
R/W
2
1
Reserved
SET_REMWU
R
R/W
0
CLR_REMWU
R/W
Note:
The mask bits do not prevent the status in the SIE_STAT register from being set, only from driving the INT3
line of the 8051 core high.
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