參數(shù)資料
型號(hào): UPD780021AYGC-XXX-8BS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, PLASTIC, LQFP-64
文件頁(yè)數(shù): 36/96頁(yè)
文件大?。?/td> 723K
代理商: UPD780021AYGC-XXX-8BS
41
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
MIN.
32
Resonator
Crystal
resonator
External
clock
Parameter
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
XT1 input
frequency (fXT)Note 1
XT1 input
high-/low-level width
(tXTH , tXTL)
Conditions
4.0 V
≤ VDD ≤ 5.5 V
1.8 V
≤ VDD < 4.0 V
TYP.
32.768
1.2
MAX.
35
2
10
38.5
Unit
kHz
s
kHz
Recommended Circuit
12
15
s
Subsystem Clock Oscillator Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions
1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark
For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
C3
XT2
XT1 IC
R
C4
XT1
XT2
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