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參數(shù)資料
| 型號(hào)： | UPD4990AG |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 129K |
| 代理商： | UPD4990AG |
5
μ
PD4990A
TERMINALS
Input terminals
°
DATA IN
°
CLK
°
C
0
, C
1
, C
2
°
STB
°
CS
°
OUT ENBL
Data input of 40-/52-bit shift register
Shift clock input of 40-/52-bit shift register
Command input (3 bit)
Strobe input
Chip select input (Prohibits CLK & STB)
Output control input (Makes the DATA OUT high impedance by inputting low level).
Output terminals (N-channel Open Drain)
°
DATA OUT
°
TP
Data output of 40-/52-bit shift register
Timing pulse output
Oscillation terminals
°
X
TAL
°
X
TAL
Oscillation inverter input (OSC IN)
Oscillation inverter output (OSC OUT)
Power supply terminals
°
V
DD
°
GND (V
SS
)
Plus power supply
Common line
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