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參數(shù)資料
| 型號： | UPD4990AG |
| 廠商： | NEC Corp. |
| 英文描述： | SERIAL I/O CALENDAR & CLOCK CMOS LSI |
| 中文描述： | 串行I / O日歷 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 129K |
| 代理商： | UPD4990AG |
11
μ
PD4990A
TIMING DIAGRAM FOR SETTING COMMANDS (C
0
', C
1
', C
2
', C
3
')
Figure 2.
V
DD
V
SS
= 2.0 V
t
DSU
= 1
μ
s MIN.
t
DHLD
= 1
μ
s MIN.
t
HLD
= 1
μ
s MIN.
t
STB
= 1
μ
s MIN.
t
d1
= 1
μ
s MAX. (Other than time read mode)
t
d2
= 20
μ
s MAX. (Time read mode)
Note:
Command (C
2
, C
1
, C
0
) is set to (1, 1, 1)
CS = "H"
A mode is latched by STB and held until another mode in the same group is set.
DATA
IN
CLK
Other than time read mode
Time read mode
OLD MODE
NEW COMMAND
VALID
OLD MODE
NEW MODE
NEW MODE
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
C
0
'
V
IL
t
DSU
t
DHLD
t
HLD
t
STB
t
d1
t
d2
STB
C
1
'
C
2
'
C
3
'
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