參數資料
型號： UPD4990AC-A
元件分類： 時鐘/數據恢復及定時提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDIP14
封裝： DIP-14
文件頁數： 8/51頁
文件大?。?/td> 211K
代理商： UPD4990AC-A
11
CHAPTER 2 FUNCTION SPECIFICATION
2.2 COMMAND SPECIFICATION
2.2.1 Parallel Command Mode
(1) REGISTER HOLD COMMAND (C2, C1, C0 = 0, 0, 0)
The 40 bit shift register is held. If CLK is entered, Data doesn’t shift. 1 Hz (Duty = 50 %) appears to DATA
OUT and 64 Hz appeares to TP. If
PD4990A’s mode is TEST MODE, TEST MODE is canceled when
REGISTER SHIFT COMMAND is read.
CLK
40 bit Shift Register
CK
Disable shift
Time Counter
Continue count up time counter
Divider
32 kHz
1 Hz
DATA OUT
(duty cycle 50%)
1 Hz
(2) REGISTER SHIFT COMMAND (C2, C1, C0 = 0, 0, 1)
It is able to shift data of 40 bit shift register. Data of DATA IN is loaded to shift register at positive edge of
CLK. B1 of shift register is shifted to B0 and appeares to DATA OUT.
CLK
40 bit Shift Register
CK
Shift
Time Counter
Time counter count up continually
Divider
32 kHz
1 Hz
DATA OUT
LSB of shift register
(B0. "1" or "0")
Data is shifted at positive edge of CLK.
DATA IN
D
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