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參數(shù)資料
| 型號： | UPD45128163G5-A80T-9JF |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 6/86頁 |
| 文件大小： | 774K |
| 代理商： | UPD45128163G5-A80T-9JF |
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Data Sheet E0348N10 (Ver. 1.0)
6
μ
PD45128163-T
CONTENTS
1.
2.
3.
4.
Input / Output Pin Function ........................................................................................................... 10
Commands ...................................................................................................................................... 11
Simplified State Diagram ................................................................................................................ 14
Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table............................................................................................................................ 15
4.2 DQM Truth Table..................................................................................................................................... 15
4.3 CKE Truth Table...................................................................................................................................... 15
4.4 Operative Command Table ................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
5.
6.
7.
Initialization ..................................................................................................................................... 20
Programming the Mode Register .................................................................................................. 21
Mode Register ................................................................................................................................. 22
7.1 Burst Length and Sequence ................................................................................................................. 23
8.
9.
10. Auto Precharge ............................................................................................................................... 26
10.1
Read with Auto Precharge ................................................................................................................. 26
10.2
Write with Auto Precharge ................................................................................................................. 27
11. Read / Write Command Interval ..................................................................................................... 28
11.1
Read to Read Command Interval ....................................................................................................... 28
11.2
Write to Write Command Interval ....................................................................................................... 28
11.3
Write to Read Command Interval ....................................................................................................... 29
11.4
Read to Write Command Interval ....................................................................................................... 30
12. Burst Termination ........................................................................................................................... 31
12.1
Burst Stop Command ......................................................................................................................... 31
12.2
Precharge Termination ....................................................................................................................... 32
Address Bits of Bank-Select and Precharge ................................................................................ 24
Precharge ......................................................................................................................................... 25
12.2.1 Precharge Termination in READ Cycle ................................................................................... 32
12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33
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