參數(shù)資料
型號(hào): UPD45128163G5-A80T-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 18/86頁
文件大?。?/td> 774K
代理商: UPD45128163G5-A80T-9JF
Data Sheet E0348N10 (Ver. 1.0)
18
μ
PD45128163-T
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100
μ
s or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed.
After the mode register set cycle, t
RSC
(2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1.
The sequence of Mode register programming and Refresh above may be transposed.
2.
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
相關(guān)PDF資料
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UPD45128163G5-A75T-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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UPD45128163G5-A80-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL
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