參數(shù)資料
型號: UPD30181AYF1-131-GA3
廠商: NEC Corp.
英文描述: 64-/32-BIT MICROPROCESSOR
中文描述: 64-/32-BIT微處理器
文件頁數(shù): 48/72頁
文件大小: 447K
代理商: UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
48
μ
PD30181A, 30181AY
(5) ROM, flash memory, SRAM, ISA interface (EXIBU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
TClock frequency
f
TClock
65.55
MHz
TClock cycle
t
TClock
15.26
ns
LClock frequency
f
LClock
32.78
MHz
LClock cycle
t
LClock
30.52
ns
Output delay time
t
EXD
0
12
ns
Data input setup time
t
EXS
5
ns
Data input hold time
t
EXH
0
ns
Data output float delay time
t
EXZ
10
ns
Data output setup time
(from command signal
)
t
EXCL
0
ns
IORDY input hold time
t
EXRDYH
0
ns
IOCS16# input hold time
t
EXCS16H
0
ns
DRQn# input inactive setup time
t
DRQNEG
20
ns
Remarks 1.
n = 0, 1
2.
TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals
when the RTCRST# signal changes to high level.
After releasing the RTC reset, the division ratio of TClock can be changed by setting the
PMUDIVREG register.
3.
LClock is generated by dividing Tclock in accordance with the setting of the LCLKDIV(1:0) bits of the
EXIBUCFG register in the EXIBU.
4.
The
MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the
external system bus interface.
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