- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384042 > UPD30181AYF1-131-GA3 (NEC Corp.) 64-/32-BIT MICROPROCESSOR PDF資料下載
參數(shù)資料
| 型號： | UPD30181AYF1-131-GA3 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT MICROPROCESSOR |
| 中文描述： | 64-/32-BIT微處理器 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPD30181AYF1-131-GA3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Data Sheet U16277EJ1V0DS
32
μ
PD30181A, 30181AY
(7/7)
Pin Name
(Signal Name)
Alternate-
Function Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
JTCK
Note 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTMS
Note 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDI
RMODE#
Note 1
,
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDO
Note 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTRST#
Note 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
BKTGIO#
Note 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
GPO63
VPBIAS
Hi-Z
HI-Z
Hi-Z
Hi-Z
Hi-Z
GPO62
VPLCD
HI-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
GPIO(61:54)
Note 2
A(22:15)
Hi-Z
Hi-Z
Note 3
Note 3
Note 3
GPIO(53:0)
Note 4
Hi-Z
Note 5
Hi-Z
Note 3
Note 3
Note 3
Notes 1.
This is the pin status when the N-Wire function has been set to use prohibit status via a setting for the
NWIREEN pin.
2.
When SyncFlash memory has been selected as the boot ROM, this pin can be used as the GPIO pin.
3.
The registers in the GIU can be used to set 1, 0, or high impedance.
4.
See the other pin names and alternate-function pin names.
5.
The GPIO19 and GPIO17 signals are sampled as CLKSEL(1:0) when the RTCRST# signal has
changed to high level in order to set the frequency of the CPU core’s pipeline reference clock
(AClock).
Caution
After an RTC reset, the GPIO pins are set in the input direction and input disable status is set.
Input enable status can be set by software after an RTC reset. Accordingly, there is no need to
externally add elements such as pull-up or pull-down resistors for unused GPIO pins in order to
determine the signal status. However, GPIO(61:54), which are shared with A(22:15), function as
GPIO pins only when SyncFlash memory has been selected. The status of output pins in
Hibernate mode can be specified by using software to enter the required settings in internal
registers in advance.
Remarks 1.
0: Low level, 1: High level, Hi-Z: High impedance
2.
When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD30181AYF1-131-GA3-A | 64-/32-BIT MICROPROCESSOR |
| UPD30181GM-66-8ED | 64-/32-Bit Microprocessor |
| UPD3570 | UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR |
| UPD3570D | UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR |
| UPD3571 | 5000 BIT CCD LINEAR IMAGE SENSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD30181AYF1-131-GA3-A | 制造商:Renesas 功能描述:MPU VR4181A RISC 32-Bit/64-Bit 0.25um 131MHz 3.3V 240-Pin FBGA |
| UPD30181GM-66-8ED | 制造商:NEC 制造商全稱:NEC 功能描述:64-/32-Bit Microprocessor |
| UPD30200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VR4300(TM).VR4305(TM).VR4310(TM) User＇s Manual | User＇s Manual[08/2000] |
| UPD30200GD-100MBB | 制造商:NEC Electronics Corporation 功能描述: |
| UPD30200GD-100-MBB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復。