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參數(shù)資料
| 型號(hào)： | UPD2845GR-E2 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E2 |
9
P
PD2845GR
INPUT SIGNAL DIVIDER
INPUT SIGNAL DIVIDER obtain the frequency: f
p
input to phase comparator. This circuit divides input frequency:
f
in
to obtain f
p
. This block consists of prescaler, 5 bit swallow counter, 13 bit main counter and divide-ratio control
circuit.
Setting numbers
Main counter
Swallow counter
Prescaler
M = 32 to 8 191
S = 0 to 31
P = 32, P+1 = 33
Total divide ratio
NT = S(P+1) + P(M
e
S) = PM+S = 32 M+S (M
t
S)
NT = 1 024 to 262 143
Relation between f
p
and f
in
f
p
= f
in
/(32 M+S)
(ex)
At f
p
= 5 kHz
NT = 70 M/5 k = 14 000
Therefore 14 000 32 = 437 16
fin = 70 MHz
n
M
n
S
Reference Counter
Reference Counter obtain the frequency: f
r
input to phase comparater. This circuit divides the reference
oscillating frequency: f
X’tal
of X’tal or TCXO to obtain f
r
. This block consists of 13 bit programmable reference counter
and prescaler of divide-by-2.
Setting number
13 bit programmable reference counter
R = 2 to 8 191
Total reference counter block divide ratio
RT = 2
u
R
RT = 4 to 16 382
Relation between f
r
and f
X’tal
f
r
= (f
X’tal
/2)/R
(ex)
f
r
= 5 kHz
R = (12.8 MHz/2)/5 kHz = 1 280
f
X’tal
= 12.8 MHz
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